AMBA Design Kit Technical Reference Manual - ARM Information ...

AHB ComponentsTest vector typesThe following types of test vector are associated with the test interface:Address vectorWrite vectorRead vectorControl vectorThe address for all subsequent read and write transfers is sampledby the TIC.The TIC performs an AHB write cycle, using the write datacurrently driven onto the external data bus.The TIC performs an AHB read cycle, driving the read data ontothe external data bus when it becomes valid.Internal TIC registers are set, that control the types of read andwrite transfers that are performed.Turnaround vector Used between a read cycle and a write cycle to avoid clashes onthe external data bus.The address, control, and turnaround vectors are all indicated by the same value on theTESTREQA and TESTREQB signals. You can use the following rules to determinethe type of vector that is being applied:• a read vector, or burst of read vectors, is followed by two turnaround vectors• when a single address or control vector is applied it is an address vector• when multiple address or control vectors are applied, they are all address vectorsapart from the last that is a control vector.Control vectorsThe control vector determines the types of transfer the TIC can perform, by setting thevalues of the HSIZETIC, HPROTTIC, and HLOCKTIC AHB master outputs.The default TIC bus master transfer type is:32-bit transfer widthHSIZETIC[2:0] signifies word transfer.Privileged system access HPROTTIC[3:0] signifies supervisor data access,uncacheable and unbufferable.Bit 0 of the control vector indicates if the control vector is valid. Therefore, if a controlvector is applied with bit 0 LOW, the vector is ignored and does not update the controlinformation. This mechanism enables address vectors that have bit 0 LOW to be appliedfor many cycles without updating the control information.3-14 Copyright © 2003, 2007 ARM Limited. All rights reserved. ARM DDI 0243C