AMBA Design Kit Technical Reference Manual - ARM Information ...

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Behavioral Models5.2 Internal memoryThe internal memory, IntMem32 and IntMem64, is a simple little-endian model of avariable-depth 32 or 64-bit wide on-chip SRAM that can be initialized with data froma local file.NoteInitialization is completed only once at simulation start up, and is not carried out basedon the module reset signal.Figure 5-2 shows the internal memory module.IntMemWrite controlAHBcontrolsignalregistersInitializationcontrolMemoryarrayRead controlFigure 5-2 AHB internal memory module components5.2.1 Programmer’s modelTable 5-3 lists the user-defined settings for the internal RAM moduleTable 5-3 User-defined settings for the internal RAM moduleSignalTypeDefaultsettingDescriptionFILENAME Input filename intram.dat This signal points to the local input data file that is read in afterresetMEMBITS Memory address width 12 This signal sets the number of used address bits5-4 Copyright © 2003, 2007 ARM Limited. All rights reserved. ARM DDI 0243C
Behavioral ModelsMemory initialization from local data fileOn simulation initialization, the internal memory module loads in data from the filespecified in the FileName setting. This file must be stored as an 8-character Verilog$readmemh format data file, for Verilog format models, that cannot contain more datathan the model supports. Address lines, starting with @, and single line comments,starting with //, are valid, but all other non-value characters are not. Loading starts fromaddress zero, and continues incrementing on word boundaries until an address line isfound in the file. Loading then continues from that address. All values are initialized tozero before loading is started. Example 5-1 shows an example intram.dat file.Example 5-1 intran.dat fileea00000bea000005// Data values stored at 0x00000200@000002000123456789ABCDEF5.2.2 Signal descriptionsThe internal memory module uses only AMBA signals. For a description of the AMBAsignals, see AMBA signals on page 1-3.ARM DDI 0243C Copyright © 2003, 2007 ARM Limited. All rights reserved. 5-5
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AMBA Design KitRevision: r3p0Techni
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ContentsAMBA Design Kit Technical R
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List of TablesAMBA Design Kit Techn
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List of TablesTable 4-23 WDOGPERIPH
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List of FiguresAMBA Design Kit Tech
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List of FiguresFigure 4-24 PrimeCel
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PrefaceThis preface introduces the
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PrefaceAppendix A AHB-Lite Overview
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PrefaceNumberingThe numbering conve
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Chapter 1IntroductionThis chapter d
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Introduction1.2 AMBA signalsThis se
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IntroductionSignalDirectionSlave Ma
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Introduction1.3 Product revisionsTh
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Chapter 2Functional OverviewThis ch
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Functional Overview2.2 ADK componen
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Functional OverviewPrimeCell Genera
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Functional Overview• MuxS2M• Re
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Functional Overview• AHB2:— EgM
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Functional Overview• Decoder• M
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Functional OverviewAddressNormal me
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AHB Components• 64-bit to 32-bit
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AHB Components3.2 ArbiterThe AMBA b
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AHB Components3.2.2 Signal descript
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AHB Components3.4 Master-to-slave m
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AHB Components3.6 Example retry sla
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AHB Components3.7.1 SMI programmer
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AHB ComponentsTest vector typesThe
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AHB ComponentsThe address increment
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AHB ComponentsTable 3-7 Signal desc
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AHB Components3.8 Bus matrixThis se
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AHB ComponentsThe two products are
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AHB Components Figure 3-8 BusMatrix
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AHB ComponentsNoteWhen connecting t
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AHB Components• If the Bus Matrix
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AHB ComponentsINCR bursts are treat
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AHB ComponentsFigure 3-11 on page 3
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AHB Components3.8.10 Signal descrip
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AHB ComponentsTable 3-8 Bus Matrix
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AHB ComponentsAddress0xFFFFFFFF0xF0
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AHB Components3.10 APB bridgeThe AH
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AHB Components3.10.2 AhbToAPB bridg
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AHB Components3.11 Example bus mast
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AHB ComponentsConfigurable optionsT
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AHB ComponentsAhb2Ahb (1:1)This is
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AHB ComponentsTrial synthesis of th
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AHB ComponentsAHB1AHBdecoder 1A[31:
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AHB Componentsconfirmation of compl
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AHB ComponentsMaster cancelspending
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AHB ComponentsSignal AHB bus Direct
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AHB Components3.13 Asynchronous AHB
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AHB ComponentsTable 3-13 Asynchrono
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AHB ComponentsTable 3-13 Asynchrono
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AHB ComponentsSlave responsesLocked
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AHB ComponentsThe nonvectored and d
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AHB Components7. Clear the interrup
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AHB ComponentsBits Name FunctionIRQ
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AHB ComponentsBits Name FunctionSof
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AHB ComponentsDefault Vector Addres
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AHB ComponentsTable 3-30 lists the
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AHB ComponentsPeripheral Identifica
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AHB ComponentsPrimeCell Identificat
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AHB ComponentsSignal Type Direction
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AHB ComponentsDownsizer transfersTh
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AHB ComponentsUnsupported transfers
Page 130 and 131: AHB ComponentsTable 3-43 Signal map
Page 132 and 133: AHB ComponentsInstead of reading HR
Page 134 and 135: AHB ComponentsThe funnel can only f
Page 136 and 137: AHB Components3-96 Copyright © 200
Page 138 and 139: APB Components4.1 Remap and pause c
Page 140 and 141: APB ComponentsReset Status Clear Re
Page 142 and 143: APB ComponentsPeripheral Identifica
Page 144 and 145: APB ComponentsPrimeCell Identificat
Page 146 and 147: APB ComponentsThe functionality of
Page 148 and 149: APB Components4.3 Peripheral to bri
Page 150 and 151: APB Components4.4.1 Programmer’s
Page 152 and 153: APB ComponentsWatchdog Raw Interrup
Page 154 and 155: APB ComponentsWatchdog Integration
Page 156 and 157: APB ComponentsNoteWhen you design a
Page 158 and 159: APB ComponentsThe four, 8-bit Prime
Page 160 and 161: APB Components4.5 Dual input timerT
Page 162 and 163: APB Componentsbackground load value
Page 164 and 165: APB Components• TIMCLKENx is tied
Page 166 and 167: APB ComponentsCurrent Value Registe
Page 168 and 169: APB ComponentsTable 4-31 lists the
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Page 172 and 173: APB ComponentsPeripheral Identifica
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Page 178 and 179: Behavioral Models5.1 External RAM,T
Page 182 and 183: Behavioral Models5.3 External ROMTh
Page 184 and 185: Behavioral Models5.5 AHB file reade
Page 186 and 187: Behavioral ModelsThe following AHB-
Page 188 and 189: Behavioral ModelsIf HREADY is asser
Page 190 and 191: Behavioral ModelsCycle n Cycle n+1C
Page 192 and 193: Behavioral ModelsCycle 1 Cycle 2Com
Page 194 and 195: Behavioral ModelsThis sequence perf
Page 196 and 197: Behavioral ModelsTable 5-7 Stimulus
Page 198 and 199: Behavioral ModelsField Default Valu
Page 200 and 201: Behavioral ModelsInput stimulusfile
Page 202 and 203: Behavioral ModelsEndiannessThe prep
Page 204 and 205: Behavioral ModelsTable 5-13 fm2conv
Page 206 and 207: Behavioral ModelsTable 5-16 Numberi
Page 208 and 209: Behavioral Models5.6 Test interface
Page 210 and 211: Behavioral Models5.6.2 User-defined
Page 212 and 213: PrimeCell GPIO6.1 OperationThe Prim
Page 214 and 215: PrimeCell GPIO6-4 Copyright © 2003
Page 216 and 217: AHB-Lite OverviewA.1 About AHB-Lite
Page 218 and 219: AHB-Lite OverviewTable A-1 AHB-Lite
Page 220 and 221: AHB-Lite OverviewA.3 AHB-Lite slave
Page 222 and 223: GlossaryAdvanced Peripheral Bus (AP
Page 224 and 225: Glossaryaddresses cause accesses to
Page 226: GlossaryGlossary-6 Copyright © 200
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