AMBA Design Kit Technical Reference Manual - ARM Information ...

AHB ComponentsUnsupported transfersIf an ERROR, SPLIT, or RETRY response is received from the32-bit slave, the response is passed to the 64-bit bus without delay.If this happens on the first half of the 64-bit transfer, the secondhalf of the transfer is not carried out.If a two-cycle response is received, the downsizer moduleautomatically aborts the current transfer by inserting an IDLEcycle on the 32-bit bus. If the current transfer request on the 64-bitbus is a valid transfer, NON_SEQ or SEQ, it is captured by theregisters in the downsizer module and is applied to the 32-bit AHBone cycle later. The downsizer module inserts a wait state on the64-bit bus to ensure the next transfer is not missed.If the transfer is a burst and an ERROR response is received from32-bit slave, the rest of the burst is blocked.The following transfer types are not supported by the downsizer module:Wide transfersIf the downsizer module receives a transfer request greater than 64 bitswide, with HSELS = 1, the response is undefined.Unaligned transfersUnaligned transfers are not supported.Burst blocking after errorIf an ERROR response is received from a 32-bit slave during a 64-bit burst, and if the64-bit master continues the burst, the rest of the burst is blocked. During blocking, theERROR response is fed back to the 64-bit AHB and an IDLE transfer is issued to the32-bit AHB. The blocking ends when a nonsequential transfer request is detected, or ifHSELS on the downsizer module is LOW. This feature ensures that there is nodiscontinuity in HADDR and HTRANS.The blocking does not apply to 32,16, or 8-bit transfers. In these cases, the rest of thetransfer requests pass through as normal. If a busy cycle is detected during burstblocking, the downsizer module replies with an OKAY response. However, thesubsequent sequential transfers are still blocked.3-88 Copyright © 2003, 2007 ARM Limited. All rights reserved. ARM DDI 0243C