AMBA Design Kit Technical Reference Manual - ARM Information ...

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List of TablesTable 3-21 ICINTENCLEAR Register bit assignments ............................................................. 3-73Table 3-22 ICSOFTINT Register bit assignments .................................................................... 3-74Table 3-23 ICSOFTINTCLEAR Register bit assignments ........................................................ 3-74Table 3-24 ICPROTECTION Register bit assignments ............................................................ 3-75Table 3-25 ICVECTADDR Register bit assignments ................................................................ 3-75Table 3-26 ICDEFVECTADDR Register bit assignments ......................................................... 3-76Table 3-27 ICITCR Register bit assignments ........................................................................... 3-76Table 3-28 ICITIP1 Register bit assignments ........................................................................... 3-77Table 3-29 ICITIP2 Register bit assignments ........................................................................... 3-77Table 3-30 ICITOP1 Register bit assignments ......................................................................... 3-78Table 3-31 ICITOP2 Register bit assignments ......................................................................... 3-78Table 3-32 ICPERIPHID0 Register bit assignments ................................................................. 3-79Table 3-33 ICPERIPHID1 Register bit assignments ................................................................. 3-80Table 3-34 ICPERIPHID2 Register bit assignments ................................................................. 3-80Table 3-35 ICPERIPHID3 Register bit assignments ................................................................. 3-80Table 3-36 ICPCELLID0 Register bit assignments ................................................................... 3-81Table 3-37 ICPCELLID1 Register bit assignments ................................................................... 3-82Table 3-38 ICPCELLID2 Register bit assignments ................................................................... 3-82Table 3-39 ICPCELLID3 Register bit assignments ................................................................... 3-82Table 3-40 Interrupt controller signals ...................................................................................... 3-83Table 3-41 Narrow transfer handling ........................................................................................ 3-86Table 3-42 Address line modification and data routing ............................................................. 3-87Table 3-43 Signal mapping when downsizer module is activated ............................................ 3-89Table 3-44 Downsizer interface signals .................................................................................... 3-90Table 3-45 Funnel interface signals .......................................................................................... 3-94Table 4-1 Remap and pause register summary ........................................................................ 4-2Table 4-2 RPCPERIPHID0 Register bit assignments ............................................................... 4-5Table 4-3 RPCPERIPHID1 Register bit assignments ............................................................... 4-5Table 4-4 RPCPERIPHID2 Register bit assignments ............................................................... 4-6Table 4-5 RPCPERIPHID3 Register bit assignments ............................................................... 4-6Table 4-6 RPCPCELLID0 Register bit assignments ................................................................. 4-7Table 4-7 RPCPCELLID1 Register bit assignments ................................................................. 4-7Table 4-8 RPCPCELLID2 Register bit assignments ................................................................. 4-7Table 4-9 RPCPCELLID3 Register bit assignments ................................................................. 4-8Table 4-10 Remap and pause controller signals ........................................................................ 4-8Table 4-11 Example APB slave memory map .......................................................................... 4-10Table 4-12 Peripheral ID format ................................................................................................ 4-11Table 4-13 Watchdog unit register summary ............................................................................ 4-14Table 4-14 WDOGCONTROL Register bit assignments .......................................................... 4-15Table 4-15 WDOGRIS Register bit assignments ...................................................................... 4-16Table 4-16 WDOGMIS Register bit assignments ..................................................................... 4-17Table 4-17 WDOGLOCK Register bit assignments .................................................................. 4-17Table 4-18 WDOGITCR Register bit assignments ................................................................... 4-18Table 4-19 WDOGITOP Register bit assignments ................................................................... 4-19Table 4-20 WDOGPERIPHID0 Register bit assignments ......................................................... 4-20Table 4-21 WDOGPERIPHID1 Register bit assignments ......................................................... 4-20Table 4-22 WDOGPERIPHID2 Register bit assignments ......................................................... 4-21vi Copyright © 2003, 2007 ARM Limited. All rights reserved. ARM DDI 0243C
List of TablesTable 4-23 WDOGPERIPHID3 Register bit assignments ......................................................... 4-21Table 4-24 WDOGPCELLID0 Register bit assignments ........................................................... 4-22Table 4-25 WDOGPCELLID1 Register bit assignments ........................................................... 4-22Table 4-26 WDOGPCELLID2 Register bit assignments ........................................................... 4-22Table 4-27 WDOGPCELLID3 Register bit assignments ........................................................... 4-23Table 4-28 Watchdog unit signals ............................................................................................. 4-23Table 4-29 Timer register summary .......................................................................................... 4-28Table 4-30 TIMERXCONTROL Register bit assignments ......................................................... 4-30Table 4-31 TIMERXRIS Register bit assignments .................................................................... 4-32Table 4-32 TIMERXMIS Register bit assignments .................................................................... 4-32Table 4-33 TIMERITCR Register bit assignments .................................................................... 4-33Table 4-34 TIMERITOP Register bit assignments .................................................................... 4-34Table 4-35 TIMERPERIPHID0 Register bit assignments .......................................................... 4-35Table 4-36 TIMERPERIPHID1 Register bit assignments .......................................................... 4-36Table 4-37 TIMERPERIPHID2 Register bit assignments .......................................................... 4-36Table 4-38 TIMERPERIPHID3 Register bit assignments .......................................................... 4-36Table 4-39 TIMERPCELLID0 Register bit assignments ............................................................ 4-37Table 4-40 TIMERPCELLID1 Register bit assignments ............................................................ 4-38Table 4-41 TIMERPCELLID2 Register bit assignments ............................................................ 4-38Table 4-42 TIMERPCELLID3 Register bit assignments ............................................................ 4-38Table 4-43 Timer signals ........................................................................................................... 4-39Table 5-1 User-defined settings for the external RAM module ................................................. 5-2Table 5-2 External RAM module signals ................................................................................... 5-2Table 5-3 User-defined settings for the internal RAM module .................................................. 5-4Table 5-4 User-defined settings for the external ROM module ................................................. 5-6Table 5-5 External ROM module signals ................................................................................... 5-6Table 5-6 Tube module signals ................................................................................................. 5-7Table 5-7 Stimulus command syntax ...................................................................................... 5-19Table 5-8 Command fields ...................................................................................................... 5-21Table 5-9 Characters supported by comment command ........................................................ 5-23Table 5-10 Compatibility between versions of FRM and fm2conv.pl ......................................... 5-25Table 5-11 Compatibility between versions of stimulus file and fm2conv.pl .............................. 5-25Table 5-12 Preprocessor command-line options ....................................................................... 5-26Table 5-13 fm2conv.pl error messages ..................................................................................... 5-27Table 5-14 fm2conv.pl warnings ............................................................................................... 5-28Table 5-15 Numbering scheme for bit 7, severity ...................................................................... 5-29Table 5-16 Numbering scheme for bits [6:4] and [3:2], error and warning type and subtype .... 5-30Table 5-17 Numbering scheme for bits [1:0], enumerator ......................................................... 5-31Table 5-18 Ticbox module signals ............................................................................................. 5-33Table 5-19 User-defined settings for the Ticbox module ........................................................... 5-34Table A-1 AHB-Lite interchangeability ....................................................................................... A-4ARM DDI 0243C Copyright © 2003, 2007 ARM Limited. All rights reserved. vii
Page 1 and 2: AMBA Design KitRevision: r3p0Techni
Page 3 and 4: ContentsAMBA Design Kit Technical R
Page 5: List of TablesAMBA Design Kit Techn
Page 9 and 10: List of FiguresAMBA Design Kit Tech
Page 11 and 12: List of FiguresFigure 4-24 PrimeCel
Page 13 and 14: PrefaceThis preface introduces the
Page 15 and 16: PrefaceAppendix A AHB-Lite Overview
Page 17 and 18: PrefaceNumberingThe numbering conve
Page 19 and 20: Chapter 1IntroductionThis chapter d
Page 21 and 22: Introduction1.2 AMBA signalsThis se
Page 23 and 24: IntroductionSignalDirectionSlave Ma
Page 25 and 26: Introduction1.3 Product revisionsTh
Page 27 and 28: Chapter 2Functional OverviewThis ch
Page 29 and 30: Functional Overview2.2 ADK componen
Page 32 and 33: Functional OverviewPrimeCell Genera
Page 34 and 35: Functional Overview• MuxS2M• Re
Page 36 and 37: Functional Overview• AHB2:— EgM
Page 38 and 39: Functional Overview• Decoder• M
Page 40 and 41: Functional OverviewAddressNormal me
Page 42 and 43: AHB Components• 64-bit to 32-bit
Page 44 and 45: AHB Components3.2 ArbiterThe AMBA b
Page 46 and 47: AHB Components3.2.2 Signal descript
Page 48 and 49: AHB Components3.4 Master-to-slave m
Page 50 and 51: AHB Components3.6 Example retry sla
Page 52 and 53: AHB Components3.7.1 SMI programmer
Page 54 and 55: AHB ComponentsTest vector typesThe
Page 56 and 57:
AHB ComponentsThe address increment
Page 58 and 59:
AHB ComponentsTable 3-7 Signal desc
Page 60 and 61:
AHB Components3.8 Bus matrixThis se
Page 62 and 63:
AHB ComponentsThe two products are
Page 64 and 65:
AHB Components Figure 3-8 BusMatrix
Page 66 and 67:
AHB ComponentsNoteWhen connecting t
Page 68 and 69:
AHB Components• If the Bus Matrix
Page 70 and 71:
AHB ComponentsINCR bursts are treat
Page 72 and 73:
AHB ComponentsFigure 3-11 on page 3
Page 74 and 75:
AHB Components3.8.10 Signal descrip
Page 76 and 77:
AHB ComponentsTable 3-8 Bus Matrix
Page 78 and 79:
AHB ComponentsAddress0xFFFFFFFF0xF0
Page 80 and 81:
AHB Components3.10 APB bridgeThe AH
Page 82 and 83:
AHB Components3.10.2 AhbToAPB bridg
Page 84 and 85:
AHB Components3.11 Example bus mast
Page 86 and 87:
AHB ComponentsConfigurable optionsT
Page 88 and 89:
AHB ComponentsAhb2Ahb (1:1)This is
Page 90 and 91:
AHB ComponentsTrial synthesis of th
Page 92 and 93:
AHB ComponentsAHB1AHBdecoder 1A[31:
Page 94 and 95:
AHB Componentsconfirmation of compl
Page 96 and 97:
AHB ComponentsMaster cancelspending
Page 98 and 99:
AHB ComponentsSignal AHB bus Direct
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AHB Components3.13 Asynchronous AHB
Page 102 and 103:
AHB ComponentsTable 3-13 Asynchrono
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AHB ComponentsTable 3-13 Asynchrono
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AHB ComponentsSlave responsesLocked
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AHB ComponentsThe nonvectored and d
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AHB Components7. Clear the interrup
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AHB ComponentsBits Name FunctionIRQ
Page 114 and 115:
AHB ComponentsBits Name FunctionSof
Page 116 and 117:
AHB ComponentsDefault Vector Addres
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AHB ComponentsTable 3-30 lists the
Page 120 and 121:
AHB ComponentsPeripheral Identifica
Page 122 and 123:
AHB ComponentsPrimeCell Identificat
Page 124 and 125:
AHB ComponentsSignal Type Direction
Page 126 and 127:
AHB ComponentsDownsizer transfersTh
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AHB ComponentsUnsupported transfers
Page 130 and 131:
AHB ComponentsTable 3-43 Signal map
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AHB ComponentsInstead of reading HR
Page 134 and 135:
AHB ComponentsThe funnel can only f
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AHB Components3-96 Copyright © 200
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APB Components4.1 Remap and pause c
Page 140 and 141:
APB ComponentsReset Status Clear Re
Page 142 and 143:
APB ComponentsPeripheral Identifica
Page 144 and 145:
APB ComponentsPrimeCell Identificat
Page 146 and 147:
APB ComponentsThe functionality of
Page 148 and 149:
APB Components4.3 Peripheral to bri
Page 150 and 151:
APB Components4.4.1 Programmer’s
Page 152 and 153:
APB ComponentsWatchdog Raw Interrup
Page 154 and 155:
APB ComponentsWatchdog Integration
Page 156 and 157:
APB ComponentsNoteWhen you design a
Page 158 and 159:
APB ComponentsThe four, 8-bit Prime
Page 160 and 161:
APB Components4.5 Dual input timerT
Page 162 and 163:
APB Componentsbackground load value
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APB Components• TIMCLKENx is tied
Page 166 and 167:
APB ComponentsCurrent Value Registe
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APB ComponentsTable 4-31 lists the
Page 170 and 171:
APB ComponentsTable 4-34 lists the
Page 172 and 173:
APB ComponentsPeripheral Identifica
Page 174 and 175:
APB ComponentsPrimeCell Identificat
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APB Components4-40 Copyright © 200
Page 178 and 179:
Behavioral Models5.1 External RAM,T
Page 180 and 181:
Behavioral Models5.2 Internal memor
Page 182 and 183:
Behavioral Models5.3 External ROMTh
Page 184 and 185:
Behavioral Models5.5 AHB file reade
Page 186 and 187:
Behavioral ModelsThe following AHB-
Page 188 and 189:
Behavioral ModelsIf HREADY is asser
Page 190 and 191:
Behavioral ModelsCycle n Cycle n+1C
Page 192 and 193:
Behavioral ModelsCycle 1 Cycle 2Com
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Behavioral ModelsThis sequence perf
Page 196 and 197:
Behavioral ModelsTable 5-7 Stimulus
Page 198 and 199:
Behavioral ModelsField Default Valu
Page 200 and 201:
Behavioral ModelsInput stimulusfile
Page 202 and 203:
Behavioral ModelsEndiannessThe prep
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Behavioral ModelsTable 5-13 fm2conv
Page 206 and 207:
Behavioral ModelsTable 5-16 Numberi
Page 208 and 209:
Behavioral Models5.6 Test interface
Page 210 and 211:
Behavioral Models5.6.2 User-defined
Page 212 and 213:
PrimeCell GPIO6.1 OperationThe Prim
Page 214 and 215:
PrimeCell GPIO6-4 Copyright © 2003
Page 216 and 217:
AHB-Lite OverviewA.1 About AHB-Lite
Page 218 and 219:
AHB-Lite OverviewTable A-1 AHB-Lite
Page 220 and 221:
AHB-Lite OverviewA.3 AHB-Lite slave
Page 222 and 223:
GlossaryAdvanced Peripheral Bus (AP
Page 224 and 225:
Glossaryaddresses cause accesses to
Page 226:
GlossaryGlossary-6 Copyright © 200
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