AMBA Design Kit Technical Reference Manual - ARM Information ...

AHB ComponentsTable 3-7 Signal descriptions (continued)Signal Type Direction DescriptionMCDATAOUT[31:0] Input AdditionalmemorycontrollerReserved.nHCLK Input Clock control Reserved.nSMBLS[3:0] Output Output pad Byte lane select signals, active LOW. The signals nSMBLS[3:0]select byte lanes [31:24], [23:16], [15:8], and [7:0] on the data bus.nSMDATAEN[3:0] Output Output pad Tristate input/output pad enable for the byte lanes of the externalmemory data bus SMDATA[31:0], active LOW. Enables the bytelanes [31:24], [23:16], [15:8], and [7:0] of the data busindependently.nSMOEN Output Output pad Output enable for external memory banks, active LOW.nSMWEN Output Output pad Reserved.REMAP Input System Indicates the state of the memory map:0 = reset memory map (SMCS7 mapped to SMCS0)1 = normal memory map.SCANENABLE Input System Dummy pin that is used as a dedicated scan enable input.SCANINHCLK Input System Dummy pin that is used as a dedicated HCLK scan chain input.SCANINnHCLK Input System Reserved.SCANOUTHCLK Output System Dummy pin that is used as a dedicated HCLK scan chain input.SCANOUTnHCLK Output System Reserved.SMADDR[25:0] Output Output pad External memory address bus, to external memory banks.SMBUSGNTEBI Input External busmultiplexorSMBUSREQEBI Output External busmultiplexorReserved.Reserved.SMCS[7:0] Output Output pad Chip select for external memory banks 7 to 0. The default is activeLOW.SMDATAIN[31:0] Input Input pad External input data bus used to read data from memory bank.SMDATAOUT[31:0] Input Input pad External output data used to write data from SMI to memory bank.3-18 Copyright © 2003, 2007 ARM Limited. All rights reserved. ARM DDI 0243C