AMBA Design Kit Technical Reference Manual - ARM Information ...

APB Components4.1 Remap and pause controllerThe remap and pause controller, RemapPause, is an APB slave, providing control of thesystem boot behavior and low-power wait for interrupt mode. Figure 4-1 shows a basicblock diagram of the remap and pause controller module.RemapandpausemodulePauseenablePauseoutputRemapclearRemapoutputReset statusset and clearIdentificationregisterReset statusregisterRead dataoutputFigure 4-1 Remap and pause module components4.1.1 Programmer’s modelThe base address of the remap and pause controller memory is not fixed and can bedifferent for any particular system implementation. However, the offset of any particularregister from the base address is fixed. Table 4-1 lists the remap and pause controllerregisters in base offset order.Table 4-1 Remap and pause register summaryNameBaseoffsetTypeWidthResetvalueDescriptionPause 0x00 WO - - See Pause Register on page 4-3Remap 0x04 R/W 1 0x0 See Remap Register on page 4-3ResetStatus 0x08 R/W 8 0x01 See Reset Status Register on page 4-3ResetStatusClr 0x0C WO 8 - See Reset Status Clear Register on page 4-4RpcPeriphID0 0xFE0 RO 8 0x09 See Peripheral Identification Registers on page 4-4RpcPeriphID1 0xFE4 RO 8 0x18 See Peripheral Identification Registers on page 4-44-2 Copyright © 2003, 2007 ARM Limited. All rights reserved. ARM DDI 0243C