AMBA Design Kit Technical Reference Manual - ARM Information ...

AHB ComponentsSignal AHB bus Direction DescriptionTable 3-12 Synchronous AHB-AHB bridge interface signals (continued)HCLKEN - Input This signal describes the relationship between HCLKS and HCLKM.This is HIGH for coincident edges between clocks.HCLKM 2 Input This clock times all bus transfers on AHB2. All signal timings on AHB2are related to the rising edge of HCLKM.HCLKS 1 Input This clock times all bus transfers on AHB1. All signal timings on AHB1are related to the rising edge of HCLKS.HGRANTM 2 Input This signal indicates that the bridge is currently the highest prioritymaster. Ownership of the address and control signals changes at the endof a transfer when HREADYM is HIGH, so the master gets access tothe bus when both HREADYM and HGRANTM are HIGH.HLOCKM 2 Output When HIGH, this signal indicates that the master requires locked accesson bus 2 and no other master must be granted that bus until this signalis LOW.HMASTLOCKS 1 Input When HIGH, this signal indicates that the master on bus 1 requireslocked access through the bridge and no other master must be grantedthe bus until this signal is LOW.HPROTM[3:0] 2 Output The protection control signals provide additional information about abus access and are primarily intended for use by any module that wantsto implement some level of protection.HPROTS[3:0] 1 Input The protection control signals provide additional information about abus access and are primarily intended for use by any module that wantsto implement some level of protection.HRDATAM 2 Input The read data bus, 32 or 64-bit, transfers data from the slave(s) on bus2, to the bridge, during read operations.HRDATAS 1 Output The read data bus, 32 or 64-bit, transfers data from the bridge to the busmaster during a read operation.HREADYM 2 Input When HIGH, the HREADYM signal indicates that a transfer hasfinished on bus 2. This signal can be driven LOW by a slave to extend atransfer.HREADYOUTS 1 Output When HIGH, the HREADYOUTS signal indicates that a transfer hasfinished on bus 1. This signal can be driven LOW by the bridge toextend a transfer.HREADYS 1 Input Input version of HREADYOUTS, required by the slave interface.3-58 Copyright © 2003, 2007 ARM Limited. All rights reserved. ARM DDI 0243C