AMBA Design Kit Technical Reference Manual - ARM Information ...

Glossaryaddresses cause accesses to sequential banks. This enables the delays associated withaccessing a bank to occur during the access to its adjacent bank, speeding up memorytransfers.Power-on resetProcessorRegionRegisterRemappingReservedScan chainTAPSee Cold reset.A contraction of microprocessor. A processor includes the CPU or core, plus additionalcomponents such as memory, and interfaces. These are combined as a single macrocell,that can be fabricated on an integrated circuit.A partition of instruction or data memory space.A temporary storage location used to hold binary data until it is ready to be used.Changing the address of physical memory or devices after the application has startedexecuting. This is typically done to enable RAM to replace ROM when the initializationhas been done.A field in a control register or instruction format is reserved if the field is to be definedby the implementation, or produces Unpredictable results if the contents of the field arenot zero. These fields are reserved for use in future extensions of the architecture or areimplementation-specific. All reserved bits not used by the implementation must bewritten as zero and are read as zero.A scan chain is made up of serially-connected devices that implement boundary scantechnology using a standard JTAG TAP interface. Each device contains at least one TAPcontroller containing shift registers that form the chain connected between TDI andTDO, through which test data is shifted. Processors can contain several shift registersto enable you to access selected parts of the device.See Test Access Port.Test Access Port (TAP)The collection of four mandatory terminals and one optional terminal that form theinput/output and control interface to a JTAG boundary-scan architecture. Themandatory terminals are TDI, TDO, TMS, and TCK. The optional terminal is TRST.UnalignedMemory accesses that are not appropriately word-aligned or halfword-aligned.See also Aligned.UndefinedWarm resetIndicates an instruction that generates an Undefined instruction trap. See the ARMArchitectural Reference Manual for more information on ARM exceptions.Also known as a core reset. Initializes the majority of the processor excluding the debugcontroller and debug logic. This type of reset is useful if you are using the debuggingfeatures of a processor.Glossary-4 Copyright © 2003, 2007 ARM Limited. All rights reserved. ARM DDI 0243C