AMBA Design Kit Technical Reference Manual - ARM Information ...

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AHB ComponentsMaster cancelspending transferHCLKHTRANSNONSEQ SEQ SEQ IDLE NONSEQ SEQHREADYHRESP OKAY OKAY OKAY ERROR OKAY OKAYError responsefrom slaveFigure 3-29 Error cancel timingBecause a registered bridge, except Ahb2AhbPass, cannot predict what the master willdo, it must always exhibit either a cancel or continue behavior. Because most AHBmasters continue with a pending transfer, the bridge also does this by default. Therefore,if a master that can potentially cancel a transfer on ERROR response is permitted to usethe bridge, the ErrorCanc block is required to change the bridge behavior.When an ERROR response is received by the bridge master, the ErrorCanc logicimmediately cancels any pending transfer and the ERROR response is passed back tothe originating master. If the master continues with a pending transfer and completes theburst, the ErrorCanc block suppresses the transfer and responds with an ERRORresponse to each transfer remaining in the burst. Figure 3-30 shows this.Master continueswith pending transferHCLKHTRANSHREADYNONSEQSEQSEQSEQ NONSEQ SEQHRESP OKAY OKAYOKAYERROR ERROR ERROR OKAYError responsefrom slaveError responses fromErrorCanc blockFigure 3-30 Error cancel using ErrorCanc timing3-56 Copyright © 2003, 2007 ARM Limited. All rights reserved. ARM DDI 0243C
AHB ComponentsNoteFor buffered write transfers, Ahb2Ahb bridge only, slave responses cannot be passedback to the master. The error-cancelling functionality is therefore disabled for bufferedtransfers in the Ahb2Ahb bridge. To facilitate this, the ErrorCanc logic is integrated intothe top level of the Ahb2Ahb bridge.IncrOverrideAn AHB master can only abort a burst if it receives an ERROR response or is degrantedbefore the burst is complete. If a master on AHB1, accessing a peripheral through thebridge is degranted before the burst is complete, the bridge master on AHB2 appears tohave illegally aborted the burst. Therefore, if the arbiter on AHB1 has the potential torearbitrate before a burst is complete, to avoid breaking protocol, the bridge must notgenerate fixed-length bursts. To avoid this, the IncrOverride block must be used. Thisblock overrides HBURSTM to always be INCR.NoteUnder certain circumstances, the ADK arbiter and ADK v1 revisions of the Bus Matrixarbiter might rearbitrate in mid-burst. If either of these are used, the IncrOverride blockmust be used with the bridges.3.12.5 Signal descriptionsTable 3-12 lists the interface signals for the synchronous AHB-AHB bridge.Signal AHB bus Direction DescriptionHADDRM[31:0] 2 Output The 32-bit system address bus.HADDRS[31:0] 1 Input The 32-bit system address bus.Table 3-12 Synchronous AHB-AHB bridge interface signalsHBURSTM[2:0] 2 Output Indicates if the transfer forms part of a burst. The bridge supports alltypes of transfer, that is single, incrementing, or wrapping.HBURSTS[2:0] 1 Input Indicates if the transfer forms part of a burst. The bridge supports alltypes of transfer, that is single, incrementing, or wrapping.HBUSREQM 2 Output A signal from the bridge to the arbiter, that indicates that the masterinterface requires bus 2. There is an HBUSREQ signal for each busmaster in the system.ARM DDI 0243C Copyright © 2003, 2007 ARM Limited. All rights reserved. 3-57
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AMBA Design KitRevision: r3p0Techni
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ContentsAMBA Design Kit Technical R
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List of TablesAMBA Design Kit Techn
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List of TablesTable 4-23 WDOGPERIPH
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List of FiguresAMBA Design Kit Tech
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List of FiguresFigure 4-24 PrimeCel
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PrefaceThis preface introduces the
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PrefaceAppendix A AHB-Lite Overview
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PrefaceNumberingThe numbering conve
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Chapter 1IntroductionThis chapter d
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Introduction1.2 AMBA signalsThis se
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IntroductionSignalDirectionSlave Ma
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Introduction1.3 Product revisionsTh
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Chapter 2Functional OverviewThis ch
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Functional Overview2.2 ADK componen
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Functional OverviewPrimeCell Genera
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Functional Overview• MuxS2M• Re
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Functional Overview• AHB2:— EgM
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Functional Overview• Decoder• M
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Functional OverviewAddressNormal me
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AHB Components• 64-bit to 32-bit
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AHB Components3.2 ArbiterThe AMBA b
Page 46 and 47: AHB Components3.2.2 Signal descript
Page 48 and 49: AHB Components3.4 Master-to-slave m
Page 50 and 51: AHB Components3.6 Example retry sla
Page 52 and 53: AHB Components3.7.1 SMI programmer
Page 54 and 55: AHB ComponentsTest vector typesThe
Page 56 and 57: AHB ComponentsThe address increment
Page 58 and 59: AHB ComponentsTable 3-7 Signal desc
Page 60 and 61: AHB Components3.8 Bus matrixThis se
Page 62 and 63: AHB ComponentsThe two products are
Page 64 and 65: AHB Components Figure 3-8 BusMatrix
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Page 68 and 69: AHB Components• If the Bus Matrix
Page 70 and 71: AHB ComponentsINCR bursts are treat
Page 72 and 73: AHB ComponentsFigure 3-11 on page 3
Page 74 and 75: AHB Components3.8.10 Signal descrip
Page 76 and 77: AHB ComponentsTable 3-8 Bus Matrix
Page 78 and 79: AHB ComponentsAddress0xFFFFFFFF0xF0
Page 80 and 81: AHB Components3.10 APB bridgeThe AH
Page 82 and 83: AHB Components3.10.2 AhbToAPB bridg
Page 84 and 85: AHB Components3.11 Example bus mast
Page 86 and 87: AHB ComponentsConfigurable optionsT
Page 88 and 89: AHB ComponentsAhb2Ahb (1:1)This is
Page 90 and 91: AHB ComponentsTrial synthesis of th
Page 92 and 93: AHB ComponentsAHB1AHBdecoder 1A[31:
Page 94 and 95: AHB Componentsconfirmation of compl
Page 98 and 99: AHB ComponentsSignal AHB bus Direct
Page 100 and 101: AHB Components3.13 Asynchronous AHB
Page 102 and 103: AHB ComponentsTable 3-13 Asynchrono
Page 104 and 105: AHB ComponentsTable 3-13 Asynchrono
Page 106 and 107: AHB ComponentsSlave responsesLocked
Page 108 and 109: AHB ComponentsThe nonvectored and d
Page 110 and 111: AHB Components7. Clear the interrup
Page 112 and 113: AHB ComponentsBits Name FunctionIRQ
Page 114 and 115: AHB ComponentsBits Name FunctionSof
Page 116 and 117: AHB ComponentsDefault Vector Addres
Page 118 and 119: AHB ComponentsTable 3-30 lists the
Page 120 and 121: AHB ComponentsPeripheral Identifica
Page 122 and 123: AHB ComponentsPrimeCell Identificat
Page 124 and 125: AHB ComponentsSignal Type Direction
Page 126 and 127: AHB ComponentsDownsizer transfersTh
Page 128 and 129: AHB ComponentsUnsupported transfers
Page 130 and 131: AHB ComponentsTable 3-43 Signal map
Page 132 and 133: AHB ComponentsInstead of reading HR
Page 134 and 135: AHB ComponentsThe funnel can only f
Page 136 and 137: AHB Components3-96 Copyright © 200
Page 138 and 139: APB Components4.1 Remap and pause c
Page 140 and 141: APB ComponentsReset Status Clear Re
Page 142 and 143: APB ComponentsPeripheral Identifica
Page 144 and 145: APB ComponentsPrimeCell Identificat
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APB ComponentsThe functionality of
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APB Components4.3 Peripheral to bri
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APB Components4.4.1 Programmer’s
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APB ComponentsWatchdog Raw Interrup
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APB ComponentsWatchdog Integration
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APB ComponentsNoteWhen you design a
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APB ComponentsThe four, 8-bit Prime
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APB Components4.5 Dual input timerT
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APB Componentsbackground load value
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APB Components• TIMCLKENx is tied
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APB ComponentsCurrent Value Registe
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APB ComponentsTable 4-31 lists the
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APB ComponentsTable 4-34 lists the
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APB ComponentsPeripheral Identifica
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APB ComponentsPrimeCell Identificat
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APB Components4-40 Copyright © 200
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Behavioral Models5.1 External RAM,T
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Behavioral Models5.2 Internal memor
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Behavioral Models5.3 External ROMTh
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Behavioral Models5.5 AHB file reade
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Behavioral ModelsThe following AHB-
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Behavioral ModelsIf HREADY is asser
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Behavioral ModelsCycle n Cycle n+1C
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Behavioral ModelsCycle 1 Cycle 2Com
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Behavioral ModelsThis sequence perf
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Behavioral ModelsTable 5-7 Stimulus
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Behavioral ModelsField Default Valu
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Behavioral ModelsInput stimulusfile
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Behavioral ModelsEndiannessThe prep
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Behavioral ModelsTable 5-13 fm2conv
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Behavioral ModelsTable 5-16 Numberi
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Behavioral Models5.6 Test interface
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Behavioral Models5.6.2 User-defined
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PrimeCell GPIO6.1 OperationThe Prim
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PrimeCell GPIO6-4 Copyright © 2003
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AHB-Lite OverviewA.1 About AHB-Lite
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AHB-Lite OverviewTable A-1 AHB-Lite
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AHB-Lite OverviewA.3 AHB-Lite slave
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GlossaryAdvanced Peripheral Bus (AP
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Glossaryaddresses cause accesses to
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GlossaryGlossary-6 Copyright © 200
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