AMBA Design Kit Technical Reference Manual - ARM Information ...

More documents

Recommendations

Info

APB Components• TIMCLKENx is tied HIGH and an enabled version of PCLK is fed into theTIMCLK input, giving sparse clock pulses synchronous to PCLK.This provision of two clock inputs enables the counters to continue to run while theAPB system is in a sleep state whereby PCLK is disabled. The changeover periodswhen PCLK is disabled and enabled must be handled by external system control logic,to ensure that the PCLK and TIMCLK inputs are fed with synchronous signals whenany register access is to occur.4.5.4 Programmer’s modelTable 4-29 lists the timer registers.Table 4-29 Timer register summaryNameBaseoffsetTypeWidthResetvalueDescriptionTIMER1LOAD 0x00 R/W 32 0x00000000 See Load Register on page 4-29TIMER1VALUE 0x04 RO 32 0xFFFFFFFF See Current Value Register on page 4-30TIMER1CONTROL 0x08 R/W 8 0x20 See Timer Control Register on page 4-30TIMER1INTCLR 0x0C WO - - See Interrupt Clear Register on page 4-31TIMER1RIS 0x10 RO 1 0x0 See Raw Interrupt Status Register on page 4-31TIMER1MIS 0x14 RO 1 0x0 See Interrupt Status Register on page 4-32TIMER1BGLOAD 0x18 R/W 32 0x00000000 See Background Load Register on page 4-32TIMER2LOAD 0x20 R/W 32 0x00000000 See Load Register on page 4-29TIMER2VALUE 0x24 RO 32 0xFFFFFFFF See Current Value Register on page 4-30TIMER2CONTROL 0x28 R/W 8 0x20 See Timer Control Register on page 4-30TIMER2INTCLR 0x2C WO - - See Interrupt Clear Register on page 4-31TIMER2RIS 0x30 RO 1 0x0 See Raw Interrupt Status Register on page 4-31TIMER2MIS 0x34 RO 1 0x0 See Interrupt Status Register on page 4-32TIMER2BGLOAD 0x38 R/W 32 0x00000000 See Background Load Register on page 4-32TIMERITCR 0xF00 R/W 1 0x0 See Integration Test Control Register on page 4-33TIMERITOP 0xF04 WO 2 0x0 See Integration Test Output Set Register onpage 4-334-28 Copyright © 2003, 2007 ARM Limited. All rights reserved. ARM DDI 0243C
APB ComponentsTable 4-29 Timer register summary (continued)NameBaseoffsetTypeWidthResetvalueDescriptionTIMERPERIPHID0 0xFE0 RO 8 0x04 See Peripheral Identification Register 0 on page 4-35TIMERPERIPHID1 0xFE4 RO 8 0x18 See Peripheral Identification Register 1 on page 4-36TIMERPERIPHID2 0xFE8 RO 8 0x04 See Peripheral Identification Register 2 on page 4-36TIMERPERIPHID3 0xFEC RO 8 0x00 See Peripheral Identification Register 3 on page 4-36TIMERPCELLID0 0xFF0 RO 8 0x0D See PrimeCell Identification Register 0 on page 4-37TIMERPCELLID1 0xFF4 RO 8 0xF0 See PrimeCell Identification Register 1 on page 4-38TIMERPCELLID2 0xFF8 RO 8 0x05 See PrimeCell Identification Register 2 on page 4-38TIMERPCELLID3 0xFFC RO 8 0xB1 See PrimeCell Identification Register 3 on page 4-38Load RegisterThe TIMERXLOAD Register is a 32-bit register containing the value from which thecounter is to decrement. This is the value used to reload the counter when Periodic modeis enabled, and the current count reaches zero.When this register is written to directly, the current count is immediately reset to thenew value at the next rising edge of TIMCLK that is enabled by TIMCLKEN.The value in this register is also overwritten if the TIMERXBGLOAD Register iswritten to, but the current count is not immediately affected.If values are written to both the TIMERXLOAD and TIMERXBGLOAD Registersbefore an enabled rising edge on TIMCLK, the following occurs:1. On the next enabled TIMCLK edge, the value written to the TIMERXLOADvalue replaces the current count value.2. Then, each time the counter reaches zero, the current count value is reset to thevalue written to TIMERXBGLOAD.Reading from the TIMERXLOAD Register at any time after the two writes haveoccurred retrieves the value written to TIMERXBGLOAD. That is, the value read fromTIMERXLOAD is always the value that takes effect for Periodic mode after the nexttime the counter reaches zero.ARM DDI 0243C Copyright © 2003, 2007 ARM Limited. All rights reserved. 4-29
Page 1 and 2:
AMBA Design KitRevision: r3p0Techni
Page 3 and 4:
ContentsAMBA Design Kit Technical R
Page 5 and 6:
List of TablesAMBA Design Kit Techn
Page 7 and 8:
List of TablesTable 4-23 WDOGPERIPH
Page 9 and 10:
List of FiguresAMBA Design Kit Tech
Page 11 and 12:
List of FiguresFigure 4-24 PrimeCel
Page 13 and 14:
PrefaceThis preface introduces the
Page 15 and 16:
PrefaceAppendix A AHB-Lite Overview
Page 17 and 18:
PrefaceNumberingThe numbering conve
Page 19 and 20:
Chapter 1IntroductionThis chapter d
Page 21 and 22:
Introduction1.2 AMBA signalsThis se
Page 23 and 24:
IntroductionSignalDirectionSlave Ma
Page 25 and 26:
Introduction1.3 Product revisionsTh
Page 27 and 28:
Chapter 2Functional OverviewThis ch
Page 29 and 30:
Functional Overview2.2 ADK componen
Page 32 and 33:
Functional OverviewPrimeCell Genera
Page 34 and 35:
Functional Overview• MuxS2M• Re
Page 36 and 37:
Functional Overview• AHB2:— EgM
Page 38 and 39:
Functional Overview• Decoder• M
Page 40 and 41:
Functional OverviewAddressNormal me
Page 42 and 43:
AHB Components• 64-bit to 32-bit
Page 44 and 45:
AHB Components3.2 ArbiterThe AMBA b
Page 46 and 47:
AHB Components3.2.2 Signal descript
Page 48 and 49:
AHB Components3.4 Master-to-slave m
Page 50 and 51:
AHB Components3.6 Example retry sla
Page 52 and 53:
AHB Components3.7.1 SMI programmer
Page 54 and 55:
AHB ComponentsTest vector typesThe
Page 56 and 57:
AHB ComponentsThe address increment
Page 58 and 59:
AHB ComponentsTable 3-7 Signal desc
Page 60 and 61:
AHB Components3.8 Bus matrixThis se
Page 62 and 63:
AHB ComponentsThe two products are
Page 64 and 65:
AHB Components Figure 3-8 BusMatrix
Page 66 and 67:
AHB ComponentsNoteWhen connecting t
Page 68 and 69:
AHB Components• If the Bus Matrix
Page 70 and 71:
AHB ComponentsINCR bursts are treat
Page 72 and 73:
AHB ComponentsFigure 3-11 on page 3
Page 74 and 75:
AHB Components3.8.10 Signal descrip
Page 76 and 77:
AHB ComponentsTable 3-8 Bus Matrix
Page 78 and 79:
AHB ComponentsAddress0xFFFFFFFF0xF0
Page 80 and 81:
AHB Components3.10 APB bridgeThe AH
Page 82 and 83:
AHB Components3.10.2 AhbToAPB bridg
Page 84 and 85:
AHB Components3.11 Example bus mast
Page 86 and 87:
AHB ComponentsConfigurable optionsT
Page 88 and 89:
AHB ComponentsAhb2Ahb (1:1)This is
Page 90 and 91:
AHB ComponentsTrial synthesis of th
Page 92 and 93:
AHB ComponentsAHB1AHBdecoder 1A[31:
Page 94 and 95:
AHB Componentsconfirmation of compl
Page 96 and 97:
AHB ComponentsMaster cancelspending
Page 98 and 99:
AHB ComponentsSignal AHB bus Direct
Page 100 and 101:
AHB Components3.13 Asynchronous AHB
Page 102 and 103:
AHB ComponentsTable 3-13 Asynchrono
Page 104 and 105:
AHB ComponentsTable 3-13 Asynchrono
Page 106 and 107:
AHB ComponentsSlave responsesLocked
Page 108 and 109:
AHB ComponentsThe nonvectored and d
Page 110 and 111:
AHB Components7. Clear the interrup
Page 112 and 113:
AHB ComponentsBits Name FunctionIRQ
Page 114 and 115: AHB ComponentsBits Name FunctionSof
Page 116 and 117: AHB ComponentsDefault Vector Addres
Page 118 and 119: AHB ComponentsTable 3-30 lists the
Page 120 and 121: AHB ComponentsPeripheral Identifica
Page 122 and 123: AHB ComponentsPrimeCell Identificat
Page 124 and 125: AHB ComponentsSignal Type Direction
Page 126 and 127: AHB ComponentsDownsizer transfersTh
Page 128 and 129: AHB ComponentsUnsupported transfers
Page 130 and 131: AHB ComponentsTable 3-43 Signal map
Page 132 and 133: AHB ComponentsInstead of reading HR
Page 134 and 135: AHB ComponentsThe funnel can only f
Page 136 and 137: AHB Components3-96 Copyright © 200
Page 138 and 139: APB Components4.1 Remap and pause c
Page 140 and 141: APB ComponentsReset Status Clear Re
Page 142 and 143: APB ComponentsPeripheral Identifica
Page 144 and 145: APB ComponentsPrimeCell Identificat
Page 146 and 147: APB ComponentsThe functionality of
Page 148 and 149: APB Components4.3 Peripheral to bri
Page 150 and 151: APB Components4.4.1 Programmer’s
Page 152 and 153: APB ComponentsWatchdog Raw Interrup
Page 154 and 155: APB ComponentsWatchdog Integration
Page 156 and 157: APB ComponentsNoteWhen you design a
Page 158 and 159: APB ComponentsThe four, 8-bit Prime
Page 160 and 161: APB Components4.5 Dual input timerT
Page 162 and 163: APB Componentsbackground load value
Page 166 and 167: APB ComponentsCurrent Value Registe
Page 168 and 169: APB ComponentsTable 4-31 lists the
Page 170 and 171: APB ComponentsTable 4-34 lists the
Page 172 and 173: APB ComponentsPeripheral Identifica
Page 174 and 175: APB ComponentsPrimeCell Identificat
Page 176 and 177: APB Components4-40 Copyright © 200
Page 178 and 179: Behavioral Models5.1 External RAM,T
Page 180 and 181: Behavioral Models5.2 Internal memor
Page 182 and 183: Behavioral Models5.3 External ROMTh
Page 184 and 185: Behavioral Models5.5 AHB file reade
Page 186 and 187: Behavioral ModelsThe following AHB-
Page 188 and 189: Behavioral ModelsIf HREADY is asser
Page 190 and 191: Behavioral ModelsCycle n Cycle n+1C
Page 192 and 193: Behavioral ModelsCycle 1 Cycle 2Com
Page 194 and 195: Behavioral ModelsThis sequence perf
Page 196 and 197: Behavioral ModelsTable 5-7 Stimulus
Page 198 and 199: Behavioral ModelsField Default Valu
Page 200 and 201: Behavioral ModelsInput stimulusfile
Page 202 and 203: Behavioral ModelsEndiannessThe prep
Page 204 and 205: Behavioral ModelsTable 5-13 fm2conv
Page 206 and 207: Behavioral ModelsTable 5-16 Numberi
Page 208 and 209: Behavioral Models5.6 Test interface
Page 210 and 211: Behavioral Models5.6.2 User-defined
Page 212 and 213: PrimeCell GPIO6.1 OperationThe Prim
Page 214 and 215:
PrimeCell GPIO6-4 Copyright © 2003
Page 216 and 217:
AHB-Lite OverviewA.1 About AHB-Lite
Page 218 and 219:
AHB-Lite OverviewTable A-1 AHB-Lite
Page 220 and 221:
AHB-Lite OverviewA.3 AHB-Lite slave
Page 222 and 223:
GlossaryAdvanced Peripheral Bus (AP
Page 224 and 225:
Glossaryaddresses cause accesses to
Page 226:
GlossaryGlossary-6 Copyright © 200
show all

AMBA Design Kit Technical Reference Manual - ARM Information ...

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?