AMBA Design Kit Technical Reference Manual - ARM Information ...

AHB ComponentsThe address incrementer is disabled by default and you must enable it using a controlvector before use.NoteThe control vector primarily changes signals that have the same timing as the addressbus. However, it also enables you to change the lock signal, that is actually requiredbefore the locked transfer commences. If the HLOCKTIC signal is used during testingit must be set one cycle before the transfer in which it is required. This difference intiming on the HLOCKTIC signal can, in some cases, cause an additional transfer to belocked both before and after the sequence that must in fact be locked.3.7.4 Signal descriptionsTable 3-7 lists non-AMBA signals used by the SMI. A number of pins, althoughpresent, are not used on the SMI, but are reserved for backward compatibility.Signal Type Direction DescriptionBIGENDIAN Input System Reserved.CANCELSMWAIT Input Input pad Reserved.EXTBUSMUX Input System Reserved.Table 3-7 Signal descriptionsHADDRTIC[31:0] Output AMBA AHBslaveHBURSTTIC[2:0] Output AMBA AHBslaveHBUSREQTIC Output AMBA AHBarbiterHGRANTTIC Input AMBA AHBarbiterHLOCKTIC Output AMBA AHBarbiterHPROTTIC[3:0] Output AMBA AHBslaveThe 32-bit system address bus.Indicates if the transfer forms part of a burst. The TIC alwaysperforms incrementing bursts of unspecified length.A signal from the TIC to the bus arbiter to indicate that it requiresthe bus.This signal indicates that the TIC is currently the highest prioritymaster. Ownership of the address or control signals changes at theend of the transfer when HREADYIN is HIGH.When HIGH, this signal indicates that the TIC requires lockedaccess to the bus and no other master must be granted the bus untilthis signal is LOW.The protection control signals indicate if the transfer is an opcodefetch or data access, as well as if the transfer is a Supervisor modeaccess or User mode access. These signals can also indicatewhether the current access is cacheable or unbufferable.3-16 Copyright © 2003, 2007 ARM Limited. All rights reserved. ARM DDI 0243C