AMBA Design Kit Technical Reference Manual - ARM Information ...

APB ComponentsTable 4-31 lists the register bit assignments.Table 4-31 TIMERXRIS Register bit assignmentsBits Name Function[31:1] - Reserved, read undefined, must read as zeros[0] Raw Timer Interrupt Raw interrupt status from the counterInterrupt Status RegisterThe TIMERXMIS Register is read-only. It indicates the masked interrupt status fromthe counter. This value is the logical AND of the raw interrupt status with the timerinterrupt enable bit from the Timer Control Register, and is the same value that is passedto the interrupt output pin. Figure 4-20 shows the register bit assignments.31 1 0UndefinedTimer InterruptFigure 4-20 TIMERXMIS Register bit assignmentsTable 4-32 lists the register bit assignments.Table 4-32 TIMERXMIS Register bit assignmentsBits Name Function[31:1] - Reserved, read undefined, must read as zeros[0] Timer Interrupt Enabled interrupt status from the counterBackground Load RegisterThe TIMERXBGLOAC Register is 32-bits and contains the value from which thecounter is to decrement. This is the value used to reload the counter when Periodic modeis enabled, and the current count reaches zero.This register provides an alternative method of accessing the TIMERXLOAD Register.The difference is that writes to TIMERXBGLOAD do not cause the counter toimmediately restart from the new value.4-32 Copyright © 2003, 2007 ARM Limited. All rights reserved. ARM DDI 0243C