AMBA Design Kit Technical Reference Manual - ARM Information ...

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Behavioral Models5.6.2 User-defined settingsTable 5-19 lists the user-defined settings for the Ticbox moduleTable 5-19 User-defined settings for the Ticbox moduleName Type Default setting DescriptionFILENAMEInputfilenameinfile.sim (Verilog)This points to the local input vector file that is read ina line at a time as each vector is performed.HALTONMISMATCHRead errorsettingFALSEThis controls the operation of the module when aread error is detected. When set to FALSE, a warningmessage is displayed showing the read error, and ifset to TRUE, the simulation is halted when a readerror is detected.VERBOSITYCommentdisplayTRUEControls the displaying of input vector filecomments. When set to TRUE, comments aredisplayed, and when set to FALSE, comments are notdisplayed. This does not affect the displaying of othersystem messages.5-34 Copyright © 2003, 2007 ARM Limited. All rights reserved. ARM DDI 0243C
Chapter 6PrimeCell GPIOThis chapter describes how the PrimeCell General Purpose Input/Output (GPIO) isintegrated within the ADK. It contains the following sections:• Operation on page 6-2• Integration within ADK on page 6-3.ARM DDI 0243C Copyright © 2003, 2007 ARM Limited. All rights reserved. 6-1
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AMBA Design KitRevision: r3p0Techni
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ContentsAMBA Design Kit Technical R
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List of TablesAMBA Design Kit Techn
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List of TablesTable 4-23 WDOGPERIPH
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List of FiguresAMBA Design Kit Tech
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List of FiguresFigure 4-24 PrimeCel
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PrefaceThis preface introduces the
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PrefaceAppendix A AHB-Lite Overview
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PrefaceNumberingThe numbering conve
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Chapter 1IntroductionThis chapter d
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Introduction1.2 AMBA signalsThis se
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IntroductionSignalDirectionSlave Ma
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Introduction1.3 Product revisionsTh
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Chapter 2Functional OverviewThis ch
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Functional Overview2.2 ADK componen
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Functional OverviewPrimeCell Genera
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Functional Overview• MuxS2M• Re
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Functional Overview• AHB2:— EgM
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Functional Overview• Decoder• M
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Functional OverviewAddressNormal me
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AHB Components• 64-bit to 32-bit
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AHB Components3.2 ArbiterThe AMBA b
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AHB Components3.2.2 Signal descript
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AHB Components3.4 Master-to-slave m
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AHB Components3.6 Example retry sla
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AHB Components3.7.1 SMI programmer
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AHB ComponentsTest vector typesThe
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AHB ComponentsThe address increment
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AHB ComponentsTable 3-7 Signal desc
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AHB Components3.8 Bus matrixThis se
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AHB ComponentsThe two products are
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AHB Components Figure 3-8 BusMatrix
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AHB ComponentsNoteWhen connecting t
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AHB Components• If the Bus Matrix
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AHB ComponentsINCR bursts are treat
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AHB ComponentsFigure 3-11 on page 3
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AHB Components3.8.10 Signal descrip
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AHB ComponentsTable 3-8 Bus Matrix
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AHB ComponentsAddress0xFFFFFFFF0xF0
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AHB Components3.10 APB bridgeThe AH
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AHB Components3.10.2 AhbToAPB bridg
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AHB Components3.11 Example bus mast
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AHB ComponentsConfigurable optionsT
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AHB ComponentsAhb2Ahb (1:1)This is
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AHB ComponentsTrial synthesis of th
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AHB ComponentsAHB1AHBdecoder 1A[31:
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AHB Componentsconfirmation of compl
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AHB ComponentsMaster cancelspending
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AHB ComponentsSignal AHB bus Direct
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AHB Components3.13 Asynchronous AHB
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AHB ComponentsTable 3-13 Asynchrono
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AHB ComponentsTable 3-13 Asynchrono
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AHB ComponentsSlave responsesLocked
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AHB ComponentsThe nonvectored and d
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AHB Components7. Clear the interrup
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AHB ComponentsBits Name FunctionIRQ
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AHB ComponentsBits Name FunctionSof
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AHB ComponentsDefault Vector Addres
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AHB ComponentsTable 3-30 lists the
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AHB ComponentsPeripheral Identifica
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AHB ComponentsPrimeCell Identificat
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AHB ComponentsSignal Type Direction
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AHB ComponentsDownsizer transfersTh
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AHB ComponentsUnsupported transfers
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AHB ComponentsTable 3-43 Signal map
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AHB ComponentsInstead of reading HR
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AHB ComponentsThe funnel can only f
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AHB Components3-96 Copyright © 200
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APB Components4.1 Remap and pause c
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APB ComponentsReset Status Clear Re
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APB ComponentsPeripheral Identifica
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APB ComponentsPrimeCell Identificat
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APB ComponentsThe functionality of
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APB Components4.3 Peripheral to bri
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APB Components4.4.1 Programmer’s
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APB ComponentsWatchdog Raw Interrup
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APB ComponentsWatchdog Integration
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APB ComponentsNoteWhen you design a
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APB ComponentsThe four, 8-bit Prime
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Page 166 and 167: APB ComponentsCurrent Value Registe
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Page 178 and 179: Behavioral Models5.1 External RAM,T
Page 180 and 181: Behavioral Models5.2 Internal memor
Page 182 and 183: Behavioral Models5.3 External ROMTh
Page 184 and 185: Behavioral Models5.5 AHB file reade
Page 186 and 187: Behavioral ModelsThe following AHB-
Page 188 and 189: Behavioral ModelsIf HREADY is asser
Page 190 and 191: Behavioral ModelsCycle n Cycle n+1C
Page 192 and 193: Behavioral ModelsCycle 1 Cycle 2Com
Page 194 and 195: Behavioral ModelsThis sequence perf
Page 196 and 197: Behavioral ModelsTable 5-7 Stimulus
Page 198 and 199: Behavioral ModelsField Default Valu
Page 200 and 201: Behavioral ModelsInput stimulusfile
Page 202 and 203: Behavioral ModelsEndiannessThe prep
Page 204 and 205: Behavioral ModelsTable 5-13 fm2conv
Page 206 and 207: Behavioral ModelsTable 5-16 Numberi
Page 208 and 209: Behavioral Models5.6 Test interface
Page 212 and 213: PrimeCell GPIO6.1 OperationThe Prim
Page 214 and 215: PrimeCell GPIO6-4 Copyright © 2003
Page 216 and 217: AHB-Lite OverviewA.1 About AHB-Lite
Page 218 and 219: AHB-Lite OverviewTable A-1 AHB-Lite
Page 220 and 221: AHB-Lite OverviewA.3 AHB-Lite slave
Page 222 and 223: GlossaryAdvanced Peripheral Bus (AP
Page 224 and 225: Glossaryaddresses cause accesses to
Page 226: GlossaryGlossary-6 Copyright © 200
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