AMBA Design Kit Technical Reference Manual - ARM Information ...

APB ComponentsAPBTIMCLKTIMCLKEN1TIMCLKEN2Dual input timerTestintegrationregistersIdentificationregistersFree-runningcounter 1Free-runningcounter 2AddressdecoderTIMINT1TIMINT2TIMINTCRead datagenerationTIMINTCgenerationFigure 4-15 Dual input timer components4.5.1 Functional description4.5.2 OperationTwo timers are defined as the default provided, although you can easily expand thisthrough extra instantiations of the FRC block. The same principle of simple expansionhas been applied to the register configuration, enabling more complex counters to beused. For each timer, the following modes of operation are available:Free-running modeThe counter wraps after reaching its zero value, and continues to countdown from the maximum value. This is the default mode.Periodic timer modeThe counter generates an interrupt at a constant interval, reloading theoriginal value after wrapping past zero.One-shot timer modeThe counter generates an interrupt once. When the counter reaches zero,it halts until reprogrammed by the user. This can be achieved by eitherclearing the One Shot Count bit in the control register, in which case thecount proceeds according to the selection of Free-running or Periodicmode, or by writing a new value to the Load Value register.Each timer has an identical set of registers as shown in Table 4-29 on page 4-28. Theoperation of each timer is identical. The timer is loaded by writing to the load registerand, if enabled, counts down to zero. When a counter is already running, writing to theload register causes the counter to immediately restart at the new value. Writing to theARM DDI 0243C Copyright © 2003, 2007 ARM Limited. All rights reserved. 4-25