AMBA Design Kit Technical Reference Manual - ARM Information ...

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List of FiguresFigure 3-19 Ahb2Ahb bridge ...................................................................................................... 3-48Figure 3-20 Ahb2AhbSyncDn bridge ......................................................................................... 3-48Figure 3-21 Ahb2AhbSyncUp bridge ......................................................................................... 3-49Figure 3-22 Ahb2AhbPass bridge .............................................................................................. 3-49Figure 3-23 Applications of synchronous AHB-AHB bridges ..................................................... 3-50Figure 3-24 System memory maps without address aliasing ..................................................... 3-51Figure 3-25 Address-aliasing hardware ..................................................................................... 3-52Figure 3-26 System memory maps with aliased addressing ...................................................... 3-52Figure 3-27 System memory maps with piecewise addressing ................................................. 3-53Figure 3-28 Bidirectional bridging .............................................................................................. 3-55Figure 3-29 Error cancel timing .................................................................................................. 3-56Figure 3-30 Error cancel using ErrorCanc timing ....................................................................... 3-56Figure 3-31 Asynchronous AHB-AHB bridge module components ............................................ 3-60Figure 3-32 AHB-Lite to AHB wrapper ....................................................................................... 3-65Figure 3-33 Interrupt controller components .............................................................................. 3-67Figure 3-34 ICPROTECTION Register bit assignments ............................................................ 3-74Figure 3-35 ICITCR Register bit assignments ........................................................................... 3-76Figure 3-36 ICITIP1 Register bit assignments ........................................................................... 3-77Figure 3-37 ICITOP1 Register bit assignments ......................................................................... 3-77Figure 3-38 ICPERIPHID0-3 Register bit assignments .............................................................. 3-79Figure 3-39 ICPCELLID0-3 Register bit assignments ................................................................ 3-81Figure 3-40 Downsizer module .................................................................................................. 3-85Figure 3-41 Funnel module ........................................................................................................ 3-93Figure 3-42 Typical funnel connection ....................................................................................... 3-93Figure 4-1 Remap and pause module components ................................................................... 4-2Figure 4-2 RPCPERIPHID0-3 Register bit assignment s ........................................................... 4-4Figure 4-3 RPCPCELLID0-3 Register bit assignments .............................................................. 4-6Figure 4-4 Example APB slave components .............................................................................. 4-9Figure 4-5 Peripheral to bridge multiplexor module components ............................................. 4-12Figure 4-6 Watchdog components ........................................................................................... 4-13Figure 4-7 WDOGCONTROL Register bit assignments .......................................................... 4-15Figure 4-8 WDOGRIS Register bit assignments ...................................................................... 4-16Figure 4-9 WDOGMIS Register bit assignments ..................................................................... 4-16Figure 4-10 WDOGLOCK Register bit assignments .................................................................. 4-17Figure 4-11 WDOGITCR Register bit assignments ................................................................... 4-18Figure 4-12 WDOGITOP Register bit assignments ................................................................... 4-18Figure 4-13 WDOGPERIPHID0-3 Register bit assignments ...................................................... 4-19Figure 4-14 WDOGPCELLID0-3 Register bit assignments ........................................................ 4-21Figure 4-15 Dual input timer components .................................................................................. 4-25Figure 4-16 Free-running timer block ......................................................................................... 4-26Figure 4-17 Prescale clock enable generation ........................................................................... 4-27Figure 4-18 TIMERXCONTROL Register bit assignments ........................................................ 4-30Figure 4-19 TIMERXRIS Register bit assignments .................................................................... 4-31Figure 4-20 TIMERXMIS Register bit assignments ................................................................... 4-32Figure 4-21 TIMERITCR Register bit assignments .................................................................... 4-33Figure 4-22 TIMERITOP Register bit assignments .................................................................... 4-33Figure 4-23 Peripheral identification register bit assignments ................................................... 4-34x Copyright © 2003, 2007 ARM Limited. All rights reserved. ARM DDI 0243C
List of FiguresFigure 4-24 PrimeCell identification register bit assignments ..................................................... 4-37Figure 5-1 AHB external RAM module interface diagram .......................................................... 5-2Figure 5-2 AHB internal memory module components ............................................................... 5-4Figure 5-3 External ROM module interface diagram .................................................................. 5-6Figure 5-4 Tube module interface diagram ................................................................................ 5-7Figure 5-5 File reader bus master .............................................................................................. 5-9Figure 5-6 Write command timing ............................................................................................ 5-10Figure 5-7 Read command timing ............................................................................................ 5-11Figure 5-8 Sequential command timing .................................................................................... 5-12Figure 5-9 Busy transfer timing ................................................................................................ 5-13Figure 5-10 Busy cycle timing .................................................................................................... 5-14Figure 5-11 Idle transfer timing ................................................................................................... 5-15Figure 5-12 Idle cycle timing ....................................................................................................... 5-16Figure 5-13 Poll command timing ............................................................................................... 5-17Figure 5-14 Stimulus file conversion .......................................................................................... 5-24Figure 5-15 Ticbox module interface diagram ............................................................................ 5-32Figure A-1 AHB-Lite single-master system ................................................................................. A-2Figure A-2 AHB-Lite components ............................................................................................... A-6ARM DDI 0243C Copyright © 2003, 2007 ARM Limited. All rights reserved. xi
Page 1 and 2: AMBA Design KitRevision: r3p0Techni
Page 3 and 4: ContentsAMBA Design Kit Technical R
Page 5 and 6: List of TablesAMBA Design Kit Techn
Page 7 and 8: List of TablesTable 4-23 WDOGPERIPH
Page 9: List of FiguresAMBA Design Kit Tech
Page 13 and 14: PrefaceThis preface introduces the
Page 15 and 16: PrefaceAppendix A AHB-Lite Overview
Page 17 and 18: PrefaceNumberingThe numbering conve
Page 19 and 20: Chapter 1IntroductionThis chapter d
Page 21 and 22: Introduction1.2 AMBA signalsThis se
Page 23 and 24: IntroductionSignalDirectionSlave Ma
Page 25 and 26: Introduction1.3 Product revisionsTh
Page 27 and 28: Chapter 2Functional OverviewThis ch
Page 29 and 30: Functional Overview2.2 ADK componen
Page 32 and 33: Functional OverviewPrimeCell Genera
Page 34 and 35: Functional Overview• MuxS2M• Re
Page 36 and 37: Functional Overview• AHB2:— EgM
Page 38 and 39: Functional Overview• Decoder• M
Page 40 and 41: Functional OverviewAddressNormal me
Page 42 and 43: AHB Components• 64-bit to 32-bit
Page 44 and 45: AHB Components3.2 ArbiterThe AMBA b
Page 46 and 47: AHB Components3.2.2 Signal descript
Page 48 and 49: AHB Components3.4 Master-to-slave m
Page 50 and 51: AHB Components3.6 Example retry sla
Page 52 and 53: AHB Components3.7.1 SMI programmer
Page 54 and 55: AHB ComponentsTest vector typesThe
Page 56 and 57: AHB ComponentsThe address increment
Page 58 and 59: AHB ComponentsTable 3-7 Signal desc
Page 60 and 61:
AHB Components3.8 Bus matrixThis se
Page 62 and 63:
AHB ComponentsThe two products are
Page 64 and 65:
AHB Components Figure 3-8 BusMatrix
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AHB ComponentsNoteWhen connecting t
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AHB Components• If the Bus Matrix
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AHB ComponentsINCR bursts are treat
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AHB ComponentsFigure 3-11 on page 3
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AHB Components3.8.10 Signal descrip
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AHB ComponentsTable 3-8 Bus Matrix
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AHB ComponentsAddress0xFFFFFFFF0xF0
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AHB Components3.10 APB bridgeThe AH
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AHB Components3.10.2 AhbToAPB bridg
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AHB Components3.11 Example bus mast
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AHB ComponentsConfigurable optionsT
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AHB ComponentsAhb2Ahb (1:1)This is
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AHB ComponentsTrial synthesis of th
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AHB ComponentsAHB1AHBdecoder 1A[31:
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AHB Componentsconfirmation of compl
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AHB ComponentsMaster cancelspending
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AHB ComponentsSignal AHB bus Direct
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AHB Components3.13 Asynchronous AHB
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AHB ComponentsTable 3-13 Asynchrono
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AHB ComponentsTable 3-13 Asynchrono
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AHB ComponentsSlave responsesLocked
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AHB ComponentsThe nonvectored and d
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AHB Components7. Clear the interrup
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AHB ComponentsBits Name FunctionIRQ
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AHB ComponentsBits Name FunctionSof
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AHB ComponentsDefault Vector Addres
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AHB ComponentsTable 3-30 lists the
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AHB ComponentsPeripheral Identifica
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AHB ComponentsPrimeCell Identificat
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AHB ComponentsSignal Type Direction
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AHB ComponentsDownsizer transfersTh
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AHB ComponentsUnsupported transfers
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AHB ComponentsTable 3-43 Signal map
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AHB ComponentsInstead of reading HR
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AHB ComponentsThe funnel can only f
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AHB Components3-96 Copyright © 200
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APB Components4.1 Remap and pause c
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APB ComponentsReset Status Clear Re
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APB ComponentsPeripheral Identifica
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APB ComponentsPrimeCell Identificat
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APB ComponentsThe functionality of
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APB Components4.3 Peripheral to bri
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APB Components4.4.1 Programmer’s
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APB ComponentsWatchdog Raw Interrup
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APB ComponentsWatchdog Integration
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APB ComponentsNoteWhen you design a
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APB ComponentsThe four, 8-bit Prime
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APB Components4.5 Dual input timerT
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APB Componentsbackground load value
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APB Components• TIMCLKENx is tied
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APB ComponentsCurrent Value Registe
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APB ComponentsTable 4-31 lists the
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APB ComponentsTable 4-34 lists the
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APB ComponentsPeripheral Identifica
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APB ComponentsPrimeCell Identificat
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APB Components4-40 Copyright © 200
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Behavioral Models5.1 External RAM,T
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Behavioral Models5.2 Internal memor
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Behavioral Models5.3 External ROMTh
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Behavioral Models5.5 AHB file reade
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Behavioral ModelsThe following AHB-
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Behavioral ModelsIf HREADY is asser
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Behavioral ModelsCycle n Cycle n+1C
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Behavioral ModelsCycle 1 Cycle 2Com
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Behavioral ModelsThis sequence perf
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Behavioral ModelsTable 5-7 Stimulus
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Behavioral ModelsField Default Valu
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Behavioral ModelsInput stimulusfile
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Behavioral ModelsEndiannessThe prep
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Behavioral ModelsTable 5-13 fm2conv
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Behavioral ModelsTable 5-16 Numberi
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Behavioral Models5.6 Test interface
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Behavioral Models5.6.2 User-defined
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PrimeCell GPIO6.1 OperationThe Prim
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PrimeCell GPIO6-4 Copyright © 2003
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AHB-Lite OverviewA.1 About AHB-Lite
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AHB-Lite OverviewTable A-1 AHB-Lite
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AHB-Lite OverviewA.3 AHB-Lite slave
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GlossaryAdvanced Peripheral Bus (AP
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Glossaryaddresses cause accesses to
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GlossaryGlossary-6 Copyright © 200
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