AMBA Design Kit Technical Reference Manual - ARM Information ...

APB ComponentsTable 4-1 Remap and pause register summary (continued)NameBaseoffsetTypeWidthResetvalueDescriptionRpcPeriphID2 0xFE8 RO 8 0x04 See Peripheral Identification Registers on page 4-4RpcPeriphID3 0xFEC RO 8 0x00 See Peripheral Identification Registers on page 4-4RpcPCellID0 0xFF0 RO 8 0x0D See PrimeCell Identification Registers on page 4-6RpcPCellID1 0xFF4 RO 8 0xF0 See PrimeCell Identification Registers on page 4-6RpcPCellID2 0xFF8 RO 8 0x05 See PrimeCell Identification Registers on page 4-6RpcPCellID3 0xFFC RO 8 0xB1 See PrimeCell Identification Registers on page 4-6Pause RegisterAny write to this location sets the PAUSE Register output HIGH. The exact effect ofwriting to this location is not defined, but typically this prevents the processor fromfetching further instructions until the receipt of an interrupt of a power-on reset.Remap RegisterBit 0 of the REMAP Register drives the REMAP output. This is typically used tochange the memory map from that required during boot-up to that for normal operation.This bit is cleared at reset and, when set, can only be cleared again by resetting theblock.Reset Status RegisterThe RESETSTATUS Register provides the reset status of the system. Only bit 0 isdefined in this specification, and provides the PRESETn status:• set HIGH at reset• set LOW through the ResetStatusClr register.Further bits in the RESETSTATUS register can be implemented to provide moredetailed reset information. The RESETSTATUS register has a dual mechanism forsetting and clearing bits, enabling independent bits to be altered with no knowledge ofthe other bits in the register. A write to the RESETSTATUS register has the effect ofsetting all the bits, except bit 0, that have a corresponding HIGH in the write data.ARM DDI 0243C Copyright © 2003, 2007 ARM Limited. All rights reserved. 4-3