AMBA Design Kit Technical Reference Manual - ARM Information ...

Behavioral ModelsThe write command operates as follows:Cycle 1Cycle 2The file reader sets up the control signals from the command and assertsHWRITE. HTRANS is NONSEQ to indicate the first transfer of theburst. The Data field is stored and ready to be driven during the dataphase.If HREADY is asserted, the file reader proceeds to the second controlphase.This is the first data phase in which the data is driven for the previouscycle. Unless the Burst field specifies a single transfer, the file readercalculates the next address based on the Size and Burst values.Read commandThe read command R starts a read burst and can be followed by one or more S vectors.For bursts of fixed length, the Burst field determines the number of S vectors. For burstsof undefined length, there can be any number of S vectors as long as they do not causethe address to cross a 1K boundary.Figure 5-7 shows the read command timing diagram.Cycle 1 Cycle 2CommandHADDRHTRANSRA1NONSEQHRDATAD1HWRITEHREADYFigure 5-7 Read command timingThe read command operates as follows:Cycle 1The file reader sets up the control signals from the command anddeasserts HWRITE. HTRANS is NONSEQ to indicate the first transferof a burst.ARM DDI 0243C Copyright © 2003, 2007 ARM Limited. All rights reserved. 5-11