AMBA Design Kit Technical Reference Manual - ARM Information ...

APB Components• TIMCLKENx is tied HIGH and an enabled version of PCLK is fed into theTIMCLK input, giving sparse clock pulses synchronous to PCLK.This provision of two clock inputs enables the counters to continue to run while theAPB system is in a sleep state whereby PCLK is disabled. The changeover periodswhen PCLK is disabled and enabled must be handled by external system control logic,to ensure that the PCLK and TIMCLK inputs are fed with synchronous signals whenany register access is to occur.4.5.4 Programmer’s modelTable 4-29 lists the timer registers.Table 4-29 Timer register summaryNameBaseoffsetTypeWidthResetvalueDescriptionTIMER1LOAD 0x00 R/W 32 0x00000000 See Load Register on page 4-29TIMER1VALUE 0x04 RO 32 0xFFFFFFFF See Current Value Register on page 4-30TIMER1CONTROL 0x08 R/W 8 0x20 See Timer Control Register on page 4-30TIMER1INTCLR 0x0C WO - - See Interrupt Clear Register on page 4-31TIMER1RIS 0x10 RO 1 0x0 See Raw Interrupt Status Register on page 4-31TIMER1MIS 0x14 RO 1 0x0 See Interrupt Status Register on page 4-32TIMER1BGLOAD 0x18 R/W 32 0x00000000 See Background Load Register on page 4-32TIMER2LOAD 0x20 R/W 32 0x00000000 See Load Register on page 4-29TIMER2VALUE 0x24 RO 32 0xFFFFFFFF See Current Value Register on page 4-30TIMER2CONTROL 0x28 R/W 8 0x20 See Timer Control Register on page 4-30TIMER2INTCLR 0x2C WO - - See Interrupt Clear Register on page 4-31TIMER2RIS 0x30 RO 1 0x0 See Raw Interrupt Status Register on page 4-31TIMER2MIS 0x34 RO 1 0x0 See Interrupt Status Register on page 4-32TIMER2BGLOAD 0x38 R/W 32 0x00000000 See Background Load Register on page 4-32TIMERITCR 0xF00 R/W 1 0x0 See Integration Test Control Register on page 4-33TIMERITOP 0xF04 WO 2 0x0 See Integration Test Output Set Register onpage 4-334-28 Copyright © 2003, 2007 ARM Limited. All rights reserved. ARM DDI 0243C