AMBA Design Kit Technical Reference Manual - ARM Information ...

AHB ComponentsTypically, the TIC is the highest priority AMBA bus master, and ensures test accessunder all conditions.The TIC model supports address incrementing and control vectors. This means that theTIC can automatically generate the address for burst transfers.3.7.3 TIC programmer’s modelThe TIC operates as a standard AHB bus master during system test when the externaltest pins show that the system is required to enter test mode. In this mode, the TICrequests control of the AHB and, when granted, uses the AHB to perform system tests.Table 3-4 shows the operation of the external test pins to change the TIC mode fromnormal operation into test mode.Table 3-4 Test control signals during normal operationTESTREQA TESTREQB TESTACK Description0 - 0 Normal operation1 - 0 Enter test mode request- - 1 Test mode enteredDuring system test the external test pins control the operation of the TIC. Table 3-5shows the operation of these pins.Table 3-5 Test control signals during test operationTESTREQA TESTREQB TESTACK Description- - 0 Current access incomplete1 1 1 Address vector orControl vector orTurnaround vector1 0 1 Write vector0 1 1 Read vector0 0 1 Exit test modeOn entry into test mode the TIC indicates that it has switched to the test clock input byasserting the TESTACK signal.ARM DDI 0243C Copyright © 2003, 2007 ARM Limited. All rights reserved. 3-13