AMBA Design Kit Technical Reference Manual - ARM Information ...

IntroductionSignalDirectionSlave Master Arbiter DecoderTable 1-1 AMBA AHB signals (continued)DescriptionHMASTER[3:0] Input - Output - These signals from the arbiter indicate the busmaster that is currently performing a transfer andis used by the slaves that support SPLIT transfersto determine the master that is attempting anaccess. The timing of HMASTER is aligned withthe timing of the address and control signals.HMASTLOCK Input - Output - Indicates that the current master is performing alocked sequence of transfers. This signal has thesame timing as the HMASTER signals.HPROT[3:0] Input Output - - The protection control signals provide additionalinformation about a bus access and are primarilyintended for use by any module that requires somelevel of protection.The signals indicate if the transfer is an opcodefetch or data access, as well as if the transfer is aprivileged mode access or User mode access. Forbus masters with a memory management unitthese signals also indicate whether the currentaccess is cacheable or bufferable.HRDATA[31:0] orHRDATA[63:0]Output Input - - The read data bus transfers data from bus slaves tothe bus master during read operations. ARMrecommends a minimum data bus width of 32 bits.However, you can easily extend this to enablehigher bandwidth operation.HREADYHREADYOUTInputOutputInput - Input - - - When HIGH, the HREADY signal indicates that atransfer has finished on the bus. You can drive thissignal LOW to extend a transfer.HRESETn Input Input Input Input The bus reset signal is active LOW. It resets thesystem and the bus.HRESP[1:0] Output Input Input - The transfer response provides additionalinformation on the status of a transfer. Fourdifferent responses are provided, OKAY, ERROR,RETRY, and SPLIT.1-4 Copyright © 2003, 2007 ARM Limited. All rights reserved. ARM DDI 0243C