AMBA Design Kit Technical Reference Manual - ARM Information ...

AHB ComponentsIf the ERROR response occurs in the last cycle of the burst, no blocking is generatedbecause the next transfer is an IDLE or nonsequential access. In this case, if the nextaccess is nonsequential, the downsizer module issues an IDLE cycle on the 32-bit AHBin the second cycle of the ERROR response, stores the transfer control information, andapplies it to the 32-bit AHB in the following cycle.A wait state is inserted on the 64-bit bus to enable the 32-bit bus to catch up with thetransfer.Slave responsesWhen a RETRY or SPLIT response is received, an IDLE cycle is issued to the 32-bitAHB in the second cycle of the RETRY or SPLIT response. If the response occursduring the first half of a 64-bit transfer, the second half is not completed. If the 64-bitmaster continues to output a valid transfer while the downsizer module is still selected,the transfer is stored and applied to the 32-bit AHB a cycle later. A wait state is outputto the 64-bit bus to enable the 32-bit AHB to catch up.In the case of SPLIT or RETRY responses during 64-bit transfers, the HRDATA valuereceived is unpredictable and must be ignored.Modification of control signalsTable 3-43 lists that, for both read and write transfers, the control signals are modifiedin the same way.Table 3-43 Signal mapping when downsizer module is activatedControl signalsMaster cycletypeReplaced byslave cyclesCommentsHTRANS IDLE to IDLE -BUSY to BUSY -NONSEQ to NONSEQ, followedby a SEQSEQ to SEQ, followed by aSEQNo change if transfer is 8, 16, or 32-bit.No change if transfer is 8, 16, or 32-bit.Exception for WRAP16 boundary,WRAP16 is mapped to INCR andNONSEQ is issued at 32-wordboundary.HADDR[2] = 0 to 0 then 1 No change if transfer is 8, 16, or 32-bit.= 1 - - Not permitted.ARM DDI 0243C Copyright © 2003, 2007 ARM Limited. All rights reserved. 3-89