AMBA Design Kit Technical Reference Manual - ARM Information ...

AHB ComponentsInterrupt flow sequenceThe following procedure shows the sequence for the vectored interrupt flow:1. An interrupt occurs.2. The ARM processor branches to either the IRQ or FIQ exception vector.3. If the interrupt is an IRQ, read the ICVectAddr register and branch to the interruptservice routine. This can be done using an LDR PC instruction. Reading theICVectorAddr register updates the interrupt controllers hardware priority register.4. Stack the workspace so that IRQ interrupts can be re-enabled.5. Enable the IRQ interrupts so that a higher priority can be serviced.6. Execute the Interrupt Service Routine (ISR).7. Clear the requesting interrupt in the peripheral, or write to the ICSoftIntClearregister if the request was generated by a software interrupt.8. Disable the interrupts and restore the workspace.9. Write to the ICVectAddr register. This clears the respective interrupt in theinternal interrupt priority hardware.10. Return from the interrupt. This re-enables the interrupts.Simple interrupt flowThe following procedure shows how you can use the interrupt controller without usingvectored interrupts or the interrupt priority hardware. For example, you can use it fordebugging.1. An interrupt occurs.2. Branch to IRQ or FIQ exception vector.3. Branch to the interrupt handler.4. Interrogate the ICIRQStatus register to determine the source that generated theinterrupt, and prioritize the interrupts if there are multiple active interrupt sources.This takes a number of instructions to compute.5. Branch to the correct ISR.6. Execute the ISR.ARM DDI 0243C Copyright © 2003, 2007 ARM Limited. All rights reserved. 3-69