AMBA Design Kit Technical Reference Manual - ARM Information ...

AHB Components3.8.10 Signal descriptionsTable 3-8 lists the signal list for the Bus Matrix.Table 3-8 Bus Matrix signalsSignal Direction DescriptionHCLK Input System bus clock. Logic is triggered on clock rising edge.HRESETn Input Activate low asynchronous reset.System address controlREMAP[3:0] Input System address remap control.Interface to masters (AHB slave)HADDRSx[N] Input N-bit address bus from AHB master. N can be in the range [31 to 63].HBURSTSx[2:0] Input Burst size information.HMASTERSx[3:0] Input Current active master.HMASTLOCKSx Input Indicate the transfer on the master AHB is a locked transfer.HPROTSx[3:0] Input Protection information.HRDATASx[63:0 or 31:0] Output Read data to bus master. Width configurable to be either 64-bit or 32-bitwide.HREADYOUTSx Output HREADY signal feedback to the master bus, indicating if the AHBBusMatrix module is ready for next operation.HREADYSx Input HREADY signal on the master AHB bus, indicating start/ending oftransfer.HRESPSx[1:0] Output Response from AHB BusMatrix module to AHB master. Width depends onarchitecture choice.HSELSx Input Active HIGH select signal to indicate shared slave connected to the AHBBusMatrix module is selected.HSIZESx[2:0] Input Size of the data.HWDATASx[63:0 or 31:0] Input Write data from AHB masters. Width configurable to be either 64-bit or32-bit wide.HWRITESx Input Indication of WRITE/READ operation.Interface to slaves (AHB master)3-34 Copyright © 2003, 2007 ARM Limited. All rights reserved. ARM DDI 0243C