AMBA Design Kit Technical Reference Manual - ARM Information ...

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AHB ComponentsInstead of reading HREADY from the 64-bit bus or HREADYOUT from the 32-bitslave multiplexor, the AHB slaves on the 32-bit bus must read the HREADYMgenerated from the downsizer module. This signal is multiplexed betweenHREADYOUTM, when a slave attached to the M port of the downsizer is selected,including during 64-bit to 32-bit conversion, and HREADYS, when the downsizer isnot selected.During a conversion, the 64-bit transfer is split into two 32-bit transfers and all the AHBslaves on the 32-bit AHB bus are able to read the HREADY signal generated by theactivated 32-bit slave. However, this HREADY signal must not be passed ontoHREADY in the 64-bit bus system because this requires the insertion of wait states forthe second 32-bit AHB transfer. Because of this, an additional HREADYM signalenables the AHB slave to determine when the end of an AHB transfer has occurred.3-92 Copyright © 2003, 2007 ARM Limited. All rights reserved. ARM DDI 0243C
AHB Components3.17 64-bit to 32-bit funnelThe AHB funnel, Funnel, is a data path multiplexor block used to convert a 64-bit databus to 32-bit data bus in AMBA systems. This module is used where the 32-bit slavesare to be accessed by a 64-bit master using transfers of word size or smaller. Figure 3-41shows the signal interface of the funnel module.HCLKHRESETnFunnel64-bitAHB busHREADYSHADDR2SHWDATAS[63:0]HRDATAS[63:0]AHBslaveinterfaceAHBmasterinterfaceHWDATAM[31:0]HRDATAM[31:0]32-bitAHB busFigure 3-41 Funnel module3.17.1 Programmer's modelThe funnel has a simple interface design to work with AHB devices. Only a small subsetof the AHB signals is implemented on the interface, because the other signals can beconnected directly between AHB masters and slaves.The funnel has two interfaces:• one for connection to AHB masters or an 64-bit AHB bus• a 32-bit AHB data bus interface for connection to a 32-bit AHB slave or 32-bitAHB slave bus.Figure 3-42 shows an example application of the funnel.Control64-bitAHBmaster64-bitAHB64-bit dataResponseFunnel(handling ofdata routing)32-bit data32-bitAHBslave(s)Figure 3-42 Typical funnel connectionARM DDI 0243C Copyright © 2003, 2007 ARM Limited. All rights reserved. 3-93
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AMBA Design KitRevision: r3p0Techni
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ContentsAMBA Design Kit Technical R
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List of TablesAMBA Design Kit Techn
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List of TablesTable 4-23 WDOGPERIPH
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List of FiguresAMBA Design Kit Tech
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List of FiguresFigure 4-24 PrimeCel
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PrefaceThis preface introduces the
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PrefaceAppendix A AHB-Lite Overview
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PrefaceNumberingThe numbering conve
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Chapter 1IntroductionThis chapter d
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Introduction1.2 AMBA signalsThis se
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IntroductionSignalDirectionSlave Ma
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Introduction1.3 Product revisionsTh
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Chapter 2Functional OverviewThis ch
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Functional Overview2.2 ADK componen
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Functional OverviewPrimeCell Genera
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Functional Overview• MuxS2M• Re
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Functional Overview• AHB2:— EgM
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Functional Overview• Decoder• M
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Functional OverviewAddressNormal me
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AHB Components• 64-bit to 32-bit
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AHB Components3.2 ArbiterThe AMBA b
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AHB Components3.2.2 Signal descript
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AHB Components3.4 Master-to-slave m
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AHB Components3.6 Example retry sla
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AHB Components3.7.1 SMI programmer
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AHB ComponentsTest vector typesThe
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AHB ComponentsThe address increment
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AHB ComponentsTable 3-7 Signal desc
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AHB Components3.8 Bus matrixThis se
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AHB ComponentsThe two products are
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AHB Components Figure 3-8 BusMatrix
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AHB ComponentsNoteWhen connecting t
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AHB Components• If the Bus Matrix
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AHB ComponentsINCR bursts are treat
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AHB ComponentsFigure 3-11 on page 3
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AHB Components3.8.10 Signal descrip
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AHB ComponentsTable 3-8 Bus Matrix
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AHB ComponentsAddress0xFFFFFFFF0xF0
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AHB Components3.10 APB bridgeThe AH
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Page 86 and 87: AHB ComponentsConfigurable optionsT
Page 88 and 89: AHB ComponentsAhb2Ahb (1:1)This is
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Page 92 and 93: AHB ComponentsAHB1AHBdecoder 1A[31:
Page 94 and 95: AHB Componentsconfirmation of compl
Page 96 and 97: AHB ComponentsMaster cancelspending
Page 98 and 99: AHB ComponentsSignal AHB bus Direct
Page 100 and 101: AHB Components3.13 Asynchronous AHB
Page 102 and 103: AHB ComponentsTable 3-13 Asynchrono
Page 104 and 105: AHB ComponentsTable 3-13 Asynchrono
Page 106 and 107: AHB ComponentsSlave responsesLocked
Page 108 and 109: AHB ComponentsThe nonvectored and d
Page 110 and 111: AHB Components7. Clear the interrup
Page 112 and 113: AHB ComponentsBits Name FunctionIRQ
Page 114 and 115: AHB ComponentsBits Name FunctionSof
Page 116 and 117: AHB ComponentsDefault Vector Addres
Page 118 and 119: AHB ComponentsTable 3-30 lists the
Page 120 and 121: AHB ComponentsPeripheral Identifica
Page 122 and 123: AHB ComponentsPrimeCell Identificat
Page 124 and 125: AHB ComponentsSignal Type Direction
Page 126 and 127: AHB ComponentsDownsizer transfersTh
Page 128 and 129: AHB ComponentsUnsupported transfers
Page 130 and 131: AHB ComponentsTable 3-43 Signal map
Page 134 and 135: AHB ComponentsThe funnel can only f
Page 136 and 137: AHB Components3-96 Copyright © 200
Page 138 and 139: APB Components4.1 Remap and pause c
Page 140 and 141: APB ComponentsReset Status Clear Re
Page 142 and 143: APB ComponentsPeripheral Identifica
Page 144 and 145: APB ComponentsPrimeCell Identificat
Page 146 and 147: APB ComponentsThe functionality of
Page 148 and 149: APB Components4.3 Peripheral to bri
Page 150 and 151: APB Components4.4.1 Programmer’s
Page 152 and 153: APB ComponentsWatchdog Raw Interrup
Page 154 and 155: APB ComponentsWatchdog Integration
Page 156 and 157: APB ComponentsNoteWhen you design a
Page 158 and 159: APB ComponentsThe four, 8-bit Prime
Page 160 and 161: APB Components4.5 Dual input timerT
Page 162 and 163: APB Componentsbackground load value
Page 164 and 165: APB Components• TIMCLKENx is tied
Page 166 and 167: APB ComponentsCurrent Value Registe
Page 168 and 169: APB ComponentsTable 4-31 lists the
Page 170 and 171: APB ComponentsTable 4-34 lists the
Page 172 and 173: APB ComponentsPeripheral Identifica
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Page 176 and 177: APB Components4-40 Copyright © 200
Page 178 and 179: Behavioral Models5.1 External RAM,T
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Behavioral Models5.3 External ROMTh
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Behavioral Models5.5 AHB file reade
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Behavioral ModelsThe following AHB-
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Behavioral ModelsIf HREADY is asser
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Behavioral ModelsCycle n Cycle n+1C
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Behavioral ModelsCycle 1 Cycle 2Com
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Behavioral ModelsThis sequence perf
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Behavioral ModelsTable 5-7 Stimulus
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Behavioral ModelsField Default Valu
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Behavioral ModelsInput stimulusfile
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Behavioral ModelsEndiannessThe prep
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Behavioral ModelsTable 5-13 fm2conv
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Behavioral ModelsTable 5-16 Numberi
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Behavioral Models5.6 Test interface
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Behavioral Models5.6.2 User-defined
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PrimeCell GPIO6.1 OperationThe Prim
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PrimeCell GPIO6-4 Copyright © 2003
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AHB-Lite OverviewA.1 About AHB-Lite
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AHB-Lite OverviewTable A-1 AHB-Lite
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AHB-Lite OverviewA.3 AHB-Lite slave
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GlossaryAdvanced Peripheral Bus (AP
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Glossaryaddresses cause accesses to
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GlossaryGlossary-6 Copyright © 200
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