AMBA Design Kit Technical Reference Manual - ARM Information ...

AHB Components3.1 Reset controllerThe reset controller, ResetCntl, generates the system reset signal from an external resetinput. This module is based on a state machine that is used to detect the external resetbeing asserted, and is used to generate the system reset output. Figure 3-1 shows thereset controller module block diagram.Reset controller moduleExternal resetsynchronizationWDOGRESnoutput driverState machineHRESETnoutput driverFigure 3-1 Reset controller module components3.1.1 Signal descriptionsTable 3-1 lists the non-AMBA signals used by the reset controller.Signal Type Direction DescriptionHRESETn System reset Output The system reset output.Table 3-1 Reset controller signalsnPOReset Power-on reset Input Power-on reset input. This active LOW signal causes a cold reset whenLOW. Can be asserted asynchronously to HCLK. The source of thenPOReset signal is implementation-dependent.WDOGRES Watchdog reset Input The watchdog clock domain reset input.WDOGRESn Watchdog reset Output The watchdog clock domain reset output.ARM DDI 0243C Copyright © 2003, 2007 ARM Limited. All rights reserved. 3-3