AMBA Design Kit Technical Reference Manual - ARM Information ...

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AHB ComponentsNoteWhen connecting to an output port on the Bus Matrix, the HSEL pin must be connectedto the attached slave even if there is only one slave present. If this is not done, the slavemight see spurious transfers under certain circumstances.Locked sequencesThe Bus Matrix is only designed to support locked sequences that target a single outputport. Because of this, a snooping bus across all input ports is not required. This providesarbitration for locked transfers on all layers simultaneously. In addition, the Bus Matrixis not designed to cope with a SPLIT response to a locked transfer. If this occurs, theBus Matrix correctly passes the SPLIT response back to the initiating master, but itmight then enable another master, connected to a different input port, to access theoutput port targeted by the first master.Full AHB and AHB-LiteThe Bus Matrix inherently supports both full AHB and AHB-Lite systems. However,you must take care with SPLIT responses. The Bus Matrix correctly passes back aSPLIT response, but then relies on an arbiter on the AHB layer connected to the relevantinput port to ensure that the initiating master is degranted until unsplit by the slave.3.8.6 Programmer's modelThe design of the Bus Matrix can be divided into input stage, decode stage, and outputstage as described in Block functionality on page 3-27. Figure 3-9 on page 3-27 showsan Bus Matrix design with:• four slave ports, for connection to bus masters• three master ports, for connection to slaves.3-26 Copyright © 2003, 2007 ARM Limited. All rights reserved. ARM DDI 0243C
AHB ComponentsInput stageDQDecoderOutput stageInput stageDecoderDQOutput stageInput stageDecoderDQOutput stageInput stageDecoderDQFigure 3-9 Example Bus Matrix design configuration3.8.7 Block functionalityFunctionality of the BusMatrix module is described in the following sections:• Input stage• Decode stage on page 3-28• Output stage on page 3-28.Input stageThe input stage provides the following functions:• It registers and holds an incoming transfer if the receiving slave is not able toaccept the transfer immediately.ARM DDI 0243C Copyright © 2003, 2007 ARM Limited. All rights reserved. 3-27
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AMBA Design KitRevision: r3p0Techni
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ContentsAMBA Design Kit Technical R
Page 5 and 6:
List of TablesAMBA Design Kit Techn
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List of TablesTable 4-23 WDOGPERIPH
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List of FiguresAMBA Design Kit Tech
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List of FiguresFigure 4-24 PrimeCel
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PrefaceThis preface introduces the
Page 15 and 16: PrefaceAppendix A AHB-Lite Overview
Page 17 and 18: PrefaceNumberingThe numbering conve
Page 19 and 20: Chapter 1IntroductionThis chapter d
Page 21 and 22: Introduction1.2 AMBA signalsThis se
Page 23 and 24: IntroductionSignalDirectionSlave Ma
Page 25 and 26: Introduction1.3 Product revisionsTh
Page 27 and 28: Chapter 2Functional OverviewThis ch
Page 29 and 30: Functional Overview2.2 ADK componen
Page 32 and 33: Functional OverviewPrimeCell Genera
Page 34 and 35: Functional Overview• MuxS2M• Re
Page 36 and 37: Functional Overview• AHB2:— EgM
Page 38 and 39: Functional Overview• Decoder• M
Page 40 and 41: Functional OverviewAddressNormal me
Page 42 and 43: AHB Components• 64-bit to 32-bit
Page 44 and 45: AHB Components3.2 ArbiterThe AMBA b
Page 46 and 47: AHB Components3.2.2 Signal descript
Page 48 and 49: AHB Components3.4 Master-to-slave m
Page 50 and 51: AHB Components3.6 Example retry sla
Page 52 and 53: AHB Components3.7.1 SMI programmer
Page 54 and 55: AHB ComponentsTest vector typesThe
Page 56 and 57: AHB ComponentsThe address increment
Page 58 and 59: AHB ComponentsTable 3-7 Signal desc
Page 60 and 61: AHB Components3.8 Bus matrixThis se
Page 62 and 63: AHB ComponentsThe two products are
Page 64 and 65: AHB Components Figure 3-8 BusMatrix
Page 68 and 69: AHB Components• If the Bus Matrix
Page 70 and 71: AHB ComponentsINCR bursts are treat
Page 72 and 73: AHB ComponentsFigure 3-11 on page 3
Page 74 and 75: AHB Components3.8.10 Signal descrip
Page 76 and 77: AHB ComponentsTable 3-8 Bus Matrix
Page 78 and 79: AHB ComponentsAddress0xFFFFFFFF0xF0
Page 80 and 81: AHB Components3.10 APB bridgeThe AH
Page 82 and 83: AHB Components3.10.2 AhbToAPB bridg
Page 84 and 85: AHB Components3.11 Example bus mast
Page 86 and 87: AHB ComponentsConfigurable optionsT
Page 88 and 89: AHB ComponentsAhb2Ahb (1:1)This is
Page 90 and 91: AHB ComponentsTrial synthesis of th
Page 92 and 93: AHB ComponentsAHB1AHBdecoder 1A[31:
Page 94 and 95: AHB Componentsconfirmation of compl
Page 96 and 97: AHB ComponentsMaster cancelspending
Page 98 and 99: AHB ComponentsSignal AHB bus Direct
Page 100 and 101: AHB Components3.13 Asynchronous AHB
Page 102 and 103: AHB ComponentsTable 3-13 Asynchrono
Page 104 and 105: AHB ComponentsTable 3-13 Asynchrono
Page 106 and 107: AHB ComponentsSlave responsesLocked
Page 108 and 109: AHB ComponentsThe nonvectored and d
Page 110 and 111: AHB Components7. Clear the interrup
Page 112 and 113: AHB ComponentsBits Name FunctionIRQ
Page 114 and 115: AHB ComponentsBits Name FunctionSof
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AHB ComponentsDefault Vector Addres
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AHB ComponentsTable 3-30 lists the
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AHB ComponentsPeripheral Identifica
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AHB ComponentsPrimeCell Identificat
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AHB ComponentsSignal Type Direction
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AHB ComponentsDownsizer transfersTh
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AHB ComponentsUnsupported transfers
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AHB ComponentsTable 3-43 Signal map
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AHB ComponentsInstead of reading HR
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AHB ComponentsThe funnel can only f
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AHB Components3-96 Copyright © 200
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APB Components4.1 Remap and pause c
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APB ComponentsReset Status Clear Re
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APB ComponentsPeripheral Identifica
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APB ComponentsPrimeCell Identificat
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APB ComponentsThe functionality of
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APB Components4.3 Peripheral to bri
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APB Components4.4.1 Programmer’s
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APB ComponentsWatchdog Raw Interrup
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APB ComponentsWatchdog Integration
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APB ComponentsNoteWhen you design a
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APB ComponentsThe four, 8-bit Prime
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APB Components4.5 Dual input timerT
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APB Componentsbackground load value
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APB Components• TIMCLKENx is tied
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APB ComponentsCurrent Value Registe
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APB ComponentsTable 4-31 lists the
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APB ComponentsTable 4-34 lists the
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APB ComponentsPeripheral Identifica
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APB ComponentsPrimeCell Identificat
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APB Components4-40 Copyright © 200
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Behavioral Models5.1 External RAM,T
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Behavioral Models5.2 Internal memor
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Behavioral Models5.3 External ROMTh
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Behavioral Models5.5 AHB file reade
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Behavioral ModelsThe following AHB-
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Behavioral ModelsIf HREADY is asser
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Behavioral ModelsCycle n Cycle n+1C
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Behavioral ModelsCycle 1 Cycle 2Com
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Behavioral ModelsThis sequence perf
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Behavioral ModelsTable 5-7 Stimulus
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Behavioral ModelsField Default Valu
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Behavioral ModelsInput stimulusfile
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Behavioral ModelsEndiannessThe prep
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Behavioral ModelsTable 5-13 fm2conv
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Behavioral ModelsTable 5-16 Numberi
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Behavioral Models5.6 Test interface
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Behavioral Models5.6.2 User-defined
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PrimeCell GPIO6.1 OperationThe Prim
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PrimeCell GPIO6-4 Copyright © 2003
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AHB-Lite OverviewA.1 About AHB-Lite
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AHB-Lite OverviewTable A-1 AHB-Lite
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AHB-Lite OverviewA.3 AHB-Lite slave
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GlossaryAdvanced Peripheral Bus (AP
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Glossaryaddresses cause accesses to
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GlossaryGlossary-6 Copyright © 200
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