AMBA Design Kit Technical Reference Manual - ARM Information ...

AHB ComponentsFigure 3-21 Ahb2AhbSyncUp bridgeTrial synthesis of the Ahb2Ahb, Ahb2AhbSyncUp, and Ahb2AhbSyncDn bridges is targeted at aclock period of 6ns, implying a frequency of ~166MHz. The required input and outputport constraints are set as follows:Inputs Maximum setup time of 30% of clock cycle, implying 1.8ns.Outputs Maximum output valid delay of 40% of clock cycle, implying 2.4ns.NoteThese are the preferred synthesis targets, that are not always achievable depending onthe technology library used. Trial synthesis using the TSMC 0.13 library has shown thatall internal, register-to-register, paths meet the 166MHz target, but that constraints onsome ports might have to be relaxed.Ahb2AhbPass (1:1)This is a simple combinatorial bridge that connects AHB buses without incurring alatency penalty. You can use this bridge as a latency-free pin-compatible alternative tothe other bridges or where a slave gasket, such as the downsizer, is required to connectto a multi-master bus. Figure 3-22 shows the Ahb2AhbPass bridge.Ahb2AhbPassAHB1(HCLK)SlaveHTRANSoverrideMasterIncroverrideHCLKLite2AhbAHB2(HCLK)HCLKAHB-LiteHCLKFigure 3-22 Ahb2AhbPass bridgeARM DDI 0243C Copyright © 2003, 2007 ARM Limited. All rights reserved. 3-49