AMBA Design Kit Technical Reference Manual - ARM Information ...

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Contents3.8 Bus matrix ................................................................................................. 3-203.9 System decoder ........................................................................................ 3-373.10 APB bridge ............................................................................................... 3-403.11 Example bus master ................................................................................. 3-443.12 Synchronous AHB to AHB bridge ............................................................. 3-473.13 Asynchronous AHB-AHB bridge ............................................................... 3-603.14 AHB-Lite to AHB wrapper ......................................................................... 3-653.15 Interrupt controller .................................................................................... 3-673.16 64-bit to 32-bit downsizer ......................................................................... 3-853.17 64-bit to 32-bit funnel ................................................................................ 3-93Chapter 4Chapter 5Chapter 6Appendix AAPB Components4.1 Remap and pause controller ...................................................................... 4-24.2 Example APB slave .................................................................................... 4-94.3 Peripheral to bridge multiplexor ................................................................ 4-124.4 Watchdog unit ........................................................................................... 4-134.5 Dual input timer ........................................................................................ 4-24Behavioral Models5.1 External RAM, ............................................................................................ 5-25.2 Internal memory .......................................................................................... 5-45.3 External ROM ............................................................................................. 5-65.4 Tube ........................................................................................................... 5-75.5 AHB file reader master ............................................................................... 5-85.6 Test interface driver .................................................................................. 5-32PrimeCell GPIO6.1 Operation .................................................................................................... 6-26.2 Integration within ADK ................................................................................ 6-3AHB-Lite OverviewA.1 About AHB-Lite ........................................................................................... A-2A.2 AHB-Lite master ......................................................................................... A-5A.3 AHB-Lite slaves .......................................................................................... A-6Glossaryiv Copyright © 2003, 2007 ARM Limited. All rights reserved. ARM DDI 0243C
List of TablesAMBA Design Kit Technical Reference ManualChange history .............................................................................................................. iiTable 1-1 AMBA AHB signals ................................................................................................... 1-3Table 1-2 AMBA APB signals .................................................................................................... 1-6Table 3-1 Reset controller signals ............................................................................................. 3-3Table 3-2 Arbiter signals descriptions ....................................................................................... 3-6Table 3-3 Static memory bank select coding, Remap = 1 ....................................................... 3-12Table 3-4 Test control signals during normal operation .......................................................... 3-13Table 3-5 Test control signals during test operation ............................................................... 3-13Table 3-6 Control vector bit definitions .................................................................................... 3-15Table 3-7 Signal descriptions .................................................................................................. 3-16Table 3-8 Bus Matrix signals ................................................................................................... 3-34Table 3-9 Decoder module signals .......................................................................................... 3-39Table 3-10 AhbToAPB Bridge signals ....................................................................................... 3-43Table 3-11 Configurable options ............................................................................................... 3-46Table 3-12 Synchronous AHB-AHB bridge interface signals .................................................... 3-57Table 3-13 Asynchronous AHB-AHB bridge interface signals .................................................. 3-62Table 3-14 Interrupt standard configuration .............................................................................. 3-68Table 3-15 Interrupt controller registers .................................................................................... 3-70Table 3-16 ICIRQSTATUS Register bit assignments ................................................................ 3-72Table 3-17 ICFIQSTATUS Register bit assignments ................................................................ 3-72Table 3-18 ICRAWINTR Register bit assignments .................................................................... 3-72Table 3-19 ICINTSELECT Register bit assignments ................................................................ 3-73Table 3-20 ICINTENABLE Register bit assignments ................................................................ 3-73ARM DDI 0243C Copyright © 2003, 2007 ARM Limited. All rights reserved. v
Page 1 and 2: AMBA Design KitRevision: r3p0Techni
Page 3: ContentsAMBA Design Kit Technical R
Page 7 and 8: List of TablesTable 4-23 WDOGPERIPH
Page 9 and 10: List of FiguresAMBA Design Kit Tech
Page 11 and 12: List of FiguresFigure 4-24 PrimeCel
Page 13 and 14: PrefaceThis preface introduces the
Page 15 and 16: PrefaceAppendix A AHB-Lite Overview
Page 17 and 18: PrefaceNumberingThe numbering conve
Page 19 and 20: Chapter 1IntroductionThis chapter d
Page 21 and 22: Introduction1.2 AMBA signalsThis se
Page 23 and 24: IntroductionSignalDirectionSlave Ma
Page 25 and 26: Introduction1.3 Product revisionsTh
Page 27 and 28: Chapter 2Functional OverviewThis ch
Page 29 and 30: Functional Overview2.2 ADK componen
Page 32 and 33: Functional OverviewPrimeCell Genera
Page 34 and 35: Functional Overview• MuxS2M• Re
Page 36 and 37: Functional Overview• AHB2:— EgM
Page 38 and 39: Functional Overview• Decoder• M
Page 40 and 41: Functional OverviewAddressNormal me
Page 42 and 43: AHB Components• 64-bit to 32-bit
Page 44 and 45: AHB Components3.2 ArbiterThe AMBA b
Page 46 and 47: AHB Components3.2.2 Signal descript
Page 48 and 49: AHB Components3.4 Master-to-slave m
Page 50 and 51: AHB Components3.6 Example retry sla
Page 52 and 53: AHB Components3.7.1 SMI programmer
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AHB ComponentsTest vector typesThe
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AHB ComponentsThe address increment
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AHB ComponentsTable 3-7 Signal desc
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AHB Components3.8 Bus matrixThis se
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AHB ComponentsThe two products are
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AHB Components Figure 3-8 BusMatrix
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AHB ComponentsNoteWhen connecting t
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AHB Components• If the Bus Matrix
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AHB ComponentsINCR bursts are treat
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AHB ComponentsFigure 3-11 on page 3
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AHB Components3.8.10 Signal descrip
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AHB ComponentsTable 3-8 Bus Matrix
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AHB ComponentsAddress0xFFFFFFFF0xF0
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AHB Components3.10 APB bridgeThe AH
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AHB Components3.10.2 AhbToAPB bridg
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AHB Components3.11 Example bus mast
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AHB ComponentsConfigurable optionsT
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AHB ComponentsAhb2Ahb (1:1)This is
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AHB ComponentsTrial synthesis of th
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AHB ComponentsAHB1AHBdecoder 1A[31:
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AHB Componentsconfirmation of compl
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AHB ComponentsMaster cancelspending
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AHB ComponentsSignal AHB bus Direct
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AHB Components3.13 Asynchronous AHB
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AHB ComponentsTable 3-13 Asynchrono
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AHB ComponentsTable 3-13 Asynchrono
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AHB ComponentsSlave responsesLocked
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AHB ComponentsThe nonvectored and d
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AHB Components7. Clear the interrup
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AHB ComponentsBits Name FunctionIRQ
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AHB ComponentsBits Name FunctionSof
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AHB ComponentsDefault Vector Addres
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AHB ComponentsTable 3-30 lists the
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AHB ComponentsPeripheral Identifica
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AHB ComponentsPrimeCell Identificat
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AHB ComponentsSignal Type Direction
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AHB ComponentsDownsizer transfersTh
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AHB ComponentsUnsupported transfers
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AHB ComponentsTable 3-43 Signal map
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AHB ComponentsInstead of reading HR
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AHB ComponentsThe funnel can only f
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AHB Components3-96 Copyright © 200
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APB Components4.1 Remap and pause c
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APB ComponentsReset Status Clear Re
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APB ComponentsPeripheral Identifica
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APB ComponentsPrimeCell Identificat
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APB ComponentsThe functionality of
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APB Components4.3 Peripheral to bri
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APB Components4.4.1 Programmer’s
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APB ComponentsWatchdog Raw Interrup
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APB ComponentsWatchdog Integration
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APB ComponentsNoteWhen you design a
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APB ComponentsThe four, 8-bit Prime
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APB Components4.5 Dual input timerT
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APB Componentsbackground load value
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APB Components• TIMCLKENx is tied
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APB ComponentsCurrent Value Registe
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APB ComponentsTable 4-31 lists the
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APB ComponentsTable 4-34 lists the
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APB ComponentsPeripheral Identifica
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APB ComponentsPrimeCell Identificat
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APB Components4-40 Copyright © 200
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Behavioral Models5.1 External RAM,T
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Behavioral Models5.2 Internal memor
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Behavioral Models5.3 External ROMTh
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Behavioral Models5.5 AHB file reade
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Behavioral ModelsThe following AHB-
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Behavioral ModelsIf HREADY is asser
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Behavioral ModelsCycle n Cycle n+1C
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Behavioral ModelsCycle 1 Cycle 2Com
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Behavioral ModelsThis sequence perf
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Behavioral ModelsTable 5-7 Stimulus
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Behavioral ModelsField Default Valu
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Behavioral ModelsInput stimulusfile
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Behavioral ModelsEndiannessThe prep
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Behavioral ModelsTable 5-13 fm2conv
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Behavioral ModelsTable 5-16 Numberi
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Behavioral Models5.6 Test interface
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Behavioral Models5.6.2 User-defined
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PrimeCell GPIO6.1 OperationThe Prim
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PrimeCell GPIO6-4 Copyright © 2003
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AHB-Lite OverviewA.1 About AHB-Lite
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AHB-Lite OverviewTable A-1 AHB-Lite
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AHB-Lite OverviewA.3 AHB-Lite slave
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GlossaryAdvanced Peripheral Bus (AP
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Glossaryaddresses cause accesses to
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GlossaryGlossary-6 Copyright © 200
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