A Technical History of the SEI

tin’s simulator. Although this prototype software was used for demonstration purposes only, application
of the Simplex architecture principles were successfully applied on such systems as the
F-22 and F-35.
SEI Research Included Software for Parallel Hardware Architectures
Software has traditionally been written in languages that presume a single processor. Although
software has been successfully written for parallel machines, the mindset is a radical departure
from the single-processor model. Early parallel machines focused largely on applications for
which with applications had natural parallelism that could be exploited, such as matrix manipulation
and image processing. However, hardware vendors and chip manufacturers recognized that to
continue to benefit from the “Moore’s Law” curve, they would eventually need to develop general-purpose
processors with a high degree of parallelism. The SEI initiated efforts that would enable
software engineers to exploit the capabilities of those processors.
Recognizing this future need to support applications running on networks of special-purpose processors
executing concurrent tasks, the SEI initiated research in software for heterogeneous machines.
This work continued from 1985 through 1992. The heterogeneous machines targeted by
this research consisted of general-purpose processors, special-purpose processors, memory boxes,
and switches that could be configured in arbitrary logical networks. The application tasks were
independent, large-grained, concurrent programs written in various programming languages communicating
via message-passing protocols. Heterogeneous machines, such as the one assumed in
this research, pushed the leading edge of software engineering [Barbacci 1988]. By 1991, the research
focused on improving the practice of developing and maintaining distributed systems. The
SEI developed a language and methodology (Durra) ) for implementing distributed, real-time applications
on heterogeneous computer systems. The SEI also developed a runtime environment to
support distributed applications that use heterogeneous machines.
By 2009, the trend to exploit the advantages of parallelism led to the development of multicore
chips, that is, a chip-level multiprocessor (CMP). While these chips offer a significant processing
advantage that might be exploited by real-time systems requiring autonomy, such as UAVs, problems
occur when threads distributed across multiple processors must synchronize with each other,
leading to idle processors and poor utilization. Essentially, there are two aspects that must be considered:
(1) allocating and mapping a thread to a processor, and (2) determining the execution order
on that processor (i.e., scheduling). A research team composed of SEI staff and CMU professors
with extensive experience in scheduling and in practical real-time systems has been
addressing multicore scheduling [Andersson 2012a]. It is critical to develop solutions to these
problems because the current approach is either to avoid the use of multicore or to turn off all processors
except one to use the old sequential solutions. Neither alternatives enables DoD systems
to realize the advantages offered by multicore chips.
The SEI Developed Analytic Techniques and Supporting Tools for
Engineering Real-Time Systems
Modern embedded systems still involve real-time constraints, but as processing capabilities improve,
embedded systems are less processor limited in achieving their real-time objectives, even
though they are often challenged by added requirements that eat up those spare cycles. In many
applications, the result has been a move away from traditional methods toward the use of more
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