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A Technical History of the SEI

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processor utilization. The sample applications allowed <strong>the</strong>m to make <strong>the</strong> critical decision to build<br />

upon RMS instead <strong>of</strong> EDF. The result <strong>of</strong> <strong>the</strong>ir work was rate monotonic analysis (RMA).<br />

RMA is <strong>the</strong> application <strong>of</strong> generalized rate monotonic scheduling [Sha 1984]. It provides <strong>the</strong> <strong>the</strong>oretic<br />

basis to bring engineering analysis to <strong>the</strong> design <strong>of</strong> real-time applications. It requires much<br />

less information than <strong>the</strong> timeline approach and makes it much easier to accommodate integration<br />

and evolution <strong>of</strong> complex real-time systems. RMA also provides <strong>the</strong> <strong>the</strong>oretic basis to bring engineering<br />

analysis to real-time computing standards, such as languages, operating systems, middleware,<br />

and hardware bus arbitration. Experience in applying RMA to real systems motivated <strong>the</strong><br />

<strong>SEI</strong> and collaborators to evolve new analytic tools.<br />

The Consequence: Engineering<br />

Replaces Art<br />

An important factor in RMA is <strong>the</strong> ability to minimize<br />

priority inversion, where a high-priority task is blocked<br />

by a lower priority task. It helps system designers predict<br />

whe<strong>the</strong>r task deadlines will be met before costly implementation.<br />

This important factor has been instrumental<br />

in enabling RMA to influence a host <strong>of</strong> hardware and<br />

s<strong>of</strong>tware standards.<br />

Today, RMA is a basic component in real-time computing<br />

textbooks and taught in many universities, such as<br />

CMU and University <strong>of</strong> Illinois Urbana-Champaign. A<br />

companion RMA handbook provides <strong>the</strong> definitive<br />

guide for practitioners [Klein 1993]. RMA is also <strong>the</strong><br />

only real-time scheduling technology approved by <strong>the</strong><br />

Federal Aviation Administration for Level A avionic<br />

s<strong>of</strong>tware in networked control applications with distributed<br />

computers, sensors, and actuators. In o<strong>the</strong>r practical<br />

applications, <strong>the</strong> F-16 was <strong>the</strong> first Air Force aircraft<br />

that utilized generalized rate monotonic scheduling. In<br />

2000, Lockheed Martin included RMS scheduling in <strong>the</strong><br />

F-35 design baseline, as it had become an established,<br />

foundational engineering practice.<br />

The View from O<strong>the</strong>rs<br />

The navigation payload s<strong>of</strong>tware<br />

for <strong>the</strong> next block <strong>of</strong> Global Positioning<br />

System upgrade recently<br />

completed testing. ... This design<br />

would have been difficult or impossible<br />

prior to <strong>the</strong> development<br />

<strong>of</strong> rate monotonic <strong>the</strong>ory.<br />

– L. Doyle, and J. Elzey ITT,<br />

Aerospace Communication<br />

Division (p.1) [Doyle 1993]<br />

Through <strong>the</strong> development <strong>of</strong> Rate<br />

Monotonic Scheduling, we now<br />

have a system that will allow<br />

[Space Station] Freedom’s computers<br />

to budget <strong>the</strong>ir time, to<br />

choose between a variety <strong>of</strong> tasks,<br />

and decide not only which one to<br />

do first but how much time to<br />

spend in <strong>the</strong> process.<br />

– Aaron Cohen, Deputy<br />

Administrator <strong>of</strong> NASA, in<br />

an October 1992 lecture<br />

(p.3) [Cohen 1992]<br />

New Challenges: A fundamental assumption <strong>of</strong> realtime<br />

scheduling <strong>the</strong>ories, including RMA, is that <strong>the</strong><br />

worst-case execution time <strong>of</strong> a task is <strong>the</strong> same whe<strong>the</strong>r it runs alone or with o<strong>the</strong>r tasks. Processor<br />

cache memory invalidates this assumption. Current multicore architectures exacerbate this<br />

problem, because s<strong>of</strong>tware running in one core could cause severe delays in o<strong>the</strong>r cores via <strong>the</strong><br />

interference <strong>of</strong> shared last-level cache among cores. Just as RMA has changed many hardware<br />

and s<strong>of</strong>tware standards in <strong>the</strong> past, RMA <strong>of</strong>fers promise that this multicore design problem will<br />

also be fixed in <strong>the</strong> future. Currently, <strong>the</strong> University <strong>of</strong> Illinois at Urbana-Champaign is collaborating<br />

with <strong>SEI</strong> and industry to address this new challenge.<br />

CMU/<strong>SEI</strong>-2016-SR-027 | SOFTWARE ENGINEERING INSTITUTE | CARNEGIE MELLON UNIVERSITY 37<br />

Distribution Statement A: Approved for Public Release; Distribution is Unlimited

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