A Technical History of the SEI

Real-Time Multicore Scheduling
The Challenge: Taking Advantage of Multicore Chips
The trend to increase processing power has shifted from increasing the frequency of execution to
multiplying the number of processors embedded in a single chip. This trend is known as multicore
chips or chip-level multiprocessor (CMP). The increase in processing power is generated by increasing
the number of instructions that can be executed concurrently rather than by reducing the
time to execute a single instruction. Consequently, an application experiences a speedup in its execution
only if it has enough instructions that can be executed concurrently—parallelizable instructions.
The additional processor capacity made available by having additional cores in a multicore
processor can be exploited only if enough parallel instructions can be found in the
application. Unfortunately, this limitation is misaligned with the sequential programming model
prevailing in current software development practice, where application code is generally developed
as a single sequence of instructions under the assumption that they will not execute in parallel.
In many real-time systems, a fair amount of parallelization has already been exploited, but still
more is needed to cope with the growing demands of computation imposed on defense systems,
such as that imposed by the increased demand for autonomy in unmanned aerial vehicles (UAVs).
Today, real-time systems and applications have already been developed using threads that are
later scheduled with well-established schedulers to achieve predictable timing behavior. However,
the bulk of the scheduling research assumed a single core; and while multiprocessors (not multicore)
are already being used and analyzed, such systems are not yet fully understood. For instance,
there are cases of anomalies where a system with N processors can miss deadlines with a
workload that is only just enough to fill one processor [Dhall 1978]. Similar problems occur when
threads distributed across multiple processors need to synchronize with each other, leading to idle
processors and poor utilization. Essentially, there are two aspects that must be considered: (1) allocating
and mapping a thread to a processor and (2) determining the execution order on that processor;
that is, scheduling. The solution to these problems will very likely also involve a change in
the structure and in the abstractions used to develop these systems.
A Solution: Real-Time Scheduling for Multicore Processors
In 2009, the SEI began to investigate real-time scheduling for multicore processors with a focus
on analyzing the problems of task-to-core allocation, synchronization, and the relationship between
synchronization and task allocation. The focus was soon extended to analyze variations of
multicore processors that include graphical processor units (GPUs). While GPUs are typically
used to render graphics, they are often used for general parallel computation as well.
Previous work on scheduling resulted in an increase of the global scheduling utilization to 33 percent
for periodic tasks and 50 percent for aperiodic tasks [Andersson 2001, 2003]. Some other approaches
chose to use quantized assignments of processor cycles to tasks with a scheduler that
calculates a scheduling window at fixed intervals [Srinivasan 2001, Anderson 2006]. However,
none of these efforts took into account the task interactions and different tasks and application
structures. The SEI partnered with Carnegie Mellon research faculty to explore the combination
of task scheduling and task synchronization, creating a coordinated allocation and synchronization
algorithm that can obtain up to twice the utilization of non-coordinated ones [Lakshmanan 2009].
CMU/SEI-2016-SR-027 | SOFTWARE ENGINEERING INSTITUTE | CARNEGIE MELLON UNIVERSITY 46
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