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Multi-Carrier and Spread Spectrum Systems: From OFDM and MC ...

Multi-Carrier and Spread Spectrum Systems: From OFDM and MC ...

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Channel Coding <strong>and</strong> Decoding 185Bit Nodesn 1 n 2 n 3 n 4 n 5 n 6 n 7 n 8W m3 n 1Wm 1 n 1Z n1 m 1Zn 1 m3CheckNodesFigure 4-45m 1 m 2 m 3 m 4Tanner graph; bit node refresh4.4.4.3 Tanner Graph’s Bit Nodes RefreshThe outgoing values from the bit nodes n i back to the check node m j are computed asfollows (see Figure 4-45):z ni →m j= LLR(x i ) + ∑ j≠iw mj →n i. (4.78)Note that this is a soft majority vote on the value of the bit x i using all information exceptw ni →m i.After the bit nodes updates, the hard decision x i can be made for each bit by lookingat the sign of x i = sign(v ni →m i+ w ni →m i). If the hard decisions satisfy the parity checkequations, a valid codeword is found <strong>and</strong> the decoding is stopped. Otherwise anotheriteration will be started <strong>and</strong> a check node/bit node update is performed. If no convergenceis achieved after a predetermined number of iterations, the current output is given out <strong>and</strong>a decoding failure is declared.4.4.4.4 Performance <strong>and</strong> ComplexityFor very large specific codes (> 10 000 bits, similar to r<strong>and</strong>om codes) <strong>and</strong> a high numberof iterations (e.g. 50), near-Shannon performance can be achieved. For instance, in thesecond version of the DVB-S2 specifications [18] it is shown that with an LDPC codeof n = 64 800, more than 2–2.5 dB of extra coding gain compared to the classical concatenatedRS + convolutional code can be achieved. However, the length n for wirelesscommunication applications will be small due to the delay constraints. For instance, inIEEE 802.16e, the chosen maximum LDPC code length is 2304 bits.In general, like finding a good Turbo interleaver, finding a good LDPC code by simulationis difficult, since some good LDPC codes at BER = 10 −6 might not be good atBER = 10 −9 . This is due to the so-called ‘error-step’ behavior of LDPC codes, whichis difficult to predict by simulations. Therefore, a programmable hardware platform (e.g.DSP or FPGA) is usually needed parallel to simulations to test in real time the performanceof a given code.The decoding complexity depends strongly on the code length n, the number of iterations,<strong>and</strong> the soft value computation. A so-called unified architecture based on two-phase

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