Abstracts Brochure - CERN

TUPCH — Poster Session 27-Jun-06 16:00 - 18:00
IQ technique will be summarised and the control loop logic described. The hardware implementation in analogue
as well as in digital format will be presented and first test results shown. The implementation of the same logic with
both technologies will give us a perfect bench to compare, and use the better of them, for the final LLRF of the ALBA
synchrotron.
The LHC Low Level RF
The LHC RF consists in eight 400 MHz superconducting
cavities per ring, with each
cavity independently powered by a 300 kW
klystron, via a circulator. The challenge for
P. Baudrenghien, G. Hagmann, J.C. Molendijk, R. Olsen, V. Rossi,
D. Stellfeld, D. Valuch, U. Wehrle (CERN)
the Low Level is to cope with both very high beam current (more than 1A RF component) and excellent beam lifetime
(emittance growth time in excess of 25 hours). For each cavity we have a Cavity Controller rack with two VME crates
implementing a strong RF Feedback, a Tuner Loop with a new algorithm, a Klystron Ripple Loop and a Conditioning
system. In addition each ring has a Beam Control system (four VME crates) including Frequency Program, Phase
Loop, Radial Loop and Synchronization Loop. A Longitudinal Damper (dipole and quadrupole mode) acting via the
400 MHz cavities is included to reduce emittance blow-up due to filamentation following phase and energy errors at
injection. Finally an RF Synchronization system implements the bunch into bucket transfer from the SPS into each
LHC ring. When fully installed in 2007 the whole system will count over three hundreds home-designed VME cards
of twenty-three different models installed in fourty-five VME crates.
Digital Design of the LHC Low Level RF: the Tuning System for the Superconducting
Cavities
The low level RF systems for the LHC are
based extensively on digital technology, not
only to achieve the required performance and
stability but also to provide full remote con-
J.C. Molendijk, P. Baudrenghien, A. Butterworth, E. Ciapala, R.
Olsen, F. Weierud (CERN) R. Sorokoletov (JINR)
trol and diagnostics facilities needed in a machine where most of the RF system is inaccessible during operation. The
hardware is based on modular VME but with additional low noise linear power supplies and a specially designed P2
backplane for timing distribution and fast data interchange. Extensive design re-use and the use of graphic FPGA design
tools have streamlined the design process. A milestone was the test of the tuning system for the superconducting
cavities. The tuning control module is based on a 2M gate FPGA with on-board DSP. Its design and functionality are
described, including features such as automatic measurements of cavity characteristics and transient response of the
tuning system. The tuner control is used as a test bed for LHC standard software components. A full ’vertical slice’
from remote application down to the hardware has been tested. Work is ongoing on the completion of other modules
and building up the software and diagnostics facilities needed for RF system commissioning.
Low-level RF System Development for the Superconducting Cavity of NSRRC
A superconducting radio frequency (SRF)
cavity of CESR-III design was operated
sucessfully in the electron storage ring at the
M.-S. Yeh (NSRRC)
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