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<strong>eZ80</strong> <strong>CPU</strong><br />
User Manual<br />
92<br />
MUL ss<br />
Multiply<br />
Operation<br />
Description<br />
ss ← ss(low) x ss(high)<br />
The ss operand is any of BC, DE, HL, or SP. The register pair is replaced with<br />
the product of the register’s low byte multiplied by its high byte. This is a 8- by 8-<br />
bit operation with a 16-bit result, regardless of the ADL mode.<br />
Condition Bits Affected<br />
None<br />
Mnemonic Operands ADL Mode Cycles Op Codes<br />
MUL ss X 6 ED, kk, dd<br />
LD.S ss,IY+d 1 — 52, ED, kk, dd<br />
LD.L ss,IY+d 0 — 49, ED, kk, dd<br />
LD IX,IY+d X — ED, 54, dd<br />
LD.S IX,IY+d 1 — 52, ED, 54, dd<br />
LD.L IX,IY+d 0 — 49, ED, 54, dd<br />
kk = binary code 01 ss1 100 where ss identifies the BC, DE, HL, or SP register<br />
assembled as follows in the object code:<br />
Register<br />
ss<br />
BC 00<br />
DE 01<br />
HL 10<br />
SP 11<br />
UM007701-1100
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