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<strong>eZ80</strong> <strong>CPU</strong><br />
User Manual<br />
83<br />
LD r, r’<br />
Load<br />
Operation<br />
r ← r’<br />
Description<br />
The r or r’ operand is any of A, B, C, D, E, H, or L. The contents of the r’ register,<br />
which remain unchanged, are loaded into the r register.<br />
Condition Bits Affected<br />
None<br />
Mnemonic Operands ADL Mode Cycles Op Codes<br />
LD r,r’ X 1 kk,<br />
kk = binary code 01 ddd sss’ where ddd identifies the destination A, B, C, D,<br />
E, H, or L register and sss identifies the source A, B, C, D, E, H, or L register<br />
assembled as follows in the object code:<br />
Register<br />
ddd or sss<br />
A 111<br />
B 000<br />
C 001<br />
D 010<br />
E 011<br />
H 100<br />
L 101<br />
UM007701-1100
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