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<strong>eZ80</strong> <strong>CPU</strong><br />
User Manual<br />
36<br />
DEC m<br />
Decrement<br />
Operation<br />
Description:<br />
m ← m – 1<br />
The m operand is any of r, (HL), (IX+d), or (IY+d). The m operand decrements<br />
by 1. ADL mode affects operation with registers HL, IX, and IY. ADL mode may<br />
be overridden with the .S or .L suffix.<br />
Condition Bits Affected<br />
S<br />
Z<br />
H<br />
P/V<br />
N<br />
C<br />
Set if result is negative; reset otherwise.<br />
Set if result is zero; reset otherwise.<br />
Set is borrowed from Bit 4; reset otherwise.<br />
Set if operand was 80H before operation; reset otherwise.<br />
Set.<br />
Not affected.<br />
Mnemonic Operands ADL Mode Cycles Op Codes<br />
DEC r X 1 jj<br />
DEC (HL) X 4 35<br />
DEC.S (HL) 1 5 52, 35<br />
DEC.L (HL) 0 5 49, 35<br />
DEC (IX+d) X 6 DD, 35, dd<br />
DEC.S (IX+d) 1 7 52, DD, 35, dd<br />
DEC.L (IX+d) 0 7 49, DD, 35, dd<br />
DEC (IY+d) X 6 FD, 35, dd<br />
DEC.S (IY+d) 1 7 52, FD, 35, dd<br />
DEC.L (IY+d) 0 7 49, FD, 35, dd<br />
jj = binary code 00 rrr 101 where rrr identifies the A, B, C, D, E, H, or L<br />
register assembled as follows into the object code.<br />
Register<br />
rrr<br />
A 111<br />
B 000<br />
C 001<br />
D 010<br />
E 011<br />
H 100<br />
L 101<br />
UM007701-1100
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