eZ80 CPU - writeframeofmind.biz

eZ80 CPU
User Manual
4
Interrupts
Virtual Z80 Mode
ADL Mode
If ADL is cleared to zero, but MBASE contains a non-zero value, the
programming model still includes 16-bit registers and a 64KB memory space,
but this space is relocated in the 16MB memory space by MBASE. The upper
eight bits of address (23-16) are the value of the MBASE register. In this Virtual
Z80 mode, several tasks can have their own Z80 partition. The MBASE register
can only be changed while in ADL mode.
If ADL is set to 1, MBASE has no effect on memory addressing. In this mode,
the PC, BC, DE, HL, IX and IY registers are expanded from 16 to 24 bits and a
24-bit Stack Pointer Long (SPL) register replaces the 16-bit Stack Pointer Short
(SPS) register that is used in the other modes. When the processor fetches an
instruction that includes a 16-bit address or immediate data in the other modes,
it automatically fetches a 24-bit address or data.
Mode Switching
The eZ80 only switches between ADL mode and the other modes as part of a
specially-prefixed CALL, JP, RET, or RST instruction, or an interrupt or trap
operation. The MBASE register can only be changed while in ADL mode.
Interrupts allow peripheral devices to suspend CPU operation in an orderly
manner and force the CPU to start a peripheral service routine. Once the
service routine is completed, the CPU returns to the operation in which it was
interrupted.
Interrupt Enable/Disable
The eZ80 has three interrupt inputs, two software maskable interrupts and a
non-maskable interrupt. The non-maskable interrupt (NMI) cannot be disabled
by the programmer, but is accepted when the peripheral device requests it. You
can enable or disable the maskable interrupts (INT and INTV).
In the eZ80 CPU, there are two interrupt enable flags (called IEF1 and IEF2)
that you can set or reset using the Enable Interrupt (EI) and Disable Interrupt
(DI) instructions. When IEF1 is reset, a maskable interrupt cannot be accepted
by the CPU.
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