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<strong>eZ80</strong> <strong>CPU</strong><br />
User Manual<br />
42<br />
EX (SP), rr<br />
Exchange Stack and Register<br />
Operation<br />
Description<br />
If .L or (ADL and not .S)<br />
(SPL+2) ↔ rr[23:16]<br />
(SPL+1) ↔ rr[15:8]<br />
(SPL+0) ↔ rr[7:0]<br />
else<br />
(SPS+1) ↔ rr[15:8]<br />
(SPS+0) ↔ rr[7:0]<br />
rr[23:16] ← 0<br />
The contents of the specified register are exchanged with the memory location<br />
specified by the contents of the stack pointer.<br />
ADL mode affects operation with the SP, HL, IX, and IY register. ADL mode may<br />
be overridden with the .S or .L suffix.<br />
Condition Bits Affected<br />
None<br />
Mnemonic Operands ADL Mode Cycles Op Codes<br />
EX (SP),HL X 5,7 E3<br />
EX.S (SP),HL 1 6 52, E3<br />
EX.L (SP),HL 0 8 49, E3<br />
EX (SP),IX X 6,8 DD, E3<br />
EX.S (SP),IX 1 7 52, DD, E3<br />
EX.L (SP),IX 0 9 49, DD, E3<br />
EX (SP),IY X 6,8 FD, E3<br />
EX.S (SP),IY 1 7 52, FD, E3<br />
EX.L (SP),IY 0 9 49, FD, E3<br />
UM007701-1100