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<strong>eZ80</strong> <strong>CPU</strong><br />
User Manual<br />
90<br />
LEA tt, IY+d<br />
Load Effective Address<br />
Operation<br />
Description<br />
tt ← IY+d<br />
The tt operand is any of BC, DE, HL, IX, or IY. The contents of the IY register is<br />
added to the signed displacement d and the sum is loaded into the multi-byte tt<br />
register.<br />
ADL mode affects operations with the BC, DE, HL, IX, or IY register. ADL mode<br />
may be overridden with the .S or .L suffix.<br />
Condition Bits Affected<br />
None<br />
Mnemonic Operands ADL Mode Cycles Op Codes<br />
LEA ss,IY+d X — ED, kk, dd<br />
LEA.S ss,IY+d 1 — 52, ED, kk, dd<br />
LEA.L ss,IY+d 0 — 49, ED, kk, dd<br />
LEA IX,IY+d X — ED, 54, dd<br />
LEA.S IX,IY+d 1 — 52, ED, 54, dd<br />
LEA.L IX,IY+d 0 — 49, ED, 54, dd<br />
kk = binary code 00 ss0 011 where ss identifies the BC, DE, HL, or IY register<br />
assembled as follows in the object code:<br />
Register<br />
ss<br />
BC 00<br />
DE 01<br />
HL 10<br />
IY 11<br />
UM007701-1100
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