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<strong>eZ80</strong> <strong>CPU</strong><br />
User Manual<br />
112<br />
PUSH vv<br />
Push Stack<br />
Operation<br />
Description<br />
if .L or (ADL and not .S)<br />
(SPL–1) ← vv23-16<br />
(SPL–2) ← vv15-8<br />
(SPL–3) ← vv7-0<br />
SPL ← SPL – 3<br />
else<br />
(SPL–1) ← vv15-86<br />
(SPL–2) ← vv7-08<br />
SPS ← SPS – 2<br />
The vv operand is any of AF, BC, DE, HL, IX, or IY. In ADL mode, the 24-bit vv<br />
register is loaded into the three bytes at the memory location specified by the<br />
contents of SPL-3 and the SPL decrements by three. In non-ADL mode, the 16-<br />
bit vv register is loaded into the two bytes at the memory location specified by<br />
the contents of SPS-2 and the SPS increments by two. ADL mode affects<br />
operations with the AF, BC, DE, HL, IX, IY, and SP registers. ADL mode may be<br />
overridden with the .S or .L suffix.<br />
Condition Bits Affected<br />
None<br />
Mnemonic Operands ADL Mode Cycles Op Codes<br />
PUSH ss 0/1 3/4 kk<br />
PUSH.S ss 1 4 52, kk<br />
PUSH.L ss 0 5 49, kk<br />
PUSH IX 0/1 4/5 DD, E5<br />
PUSH.S IX 1 5 52, DD, E5<br />
PUSH.L IX 0 6 49, DD, E5<br />
PUSH IY 0/1 4/5 FD, E5<br />
PUSH.S IY 1 5 52, FD, E5<br />
PUSH.L IY 0 6 49, FD, E5<br />
kk = binary code 11 ss0 101 where ss identifies the AF, BC, DE, or HL register<br />
assembled as follows into the object code:<br />
Register ss<br />
AF 11<br />
BC 00<br />
DE 01<br />
HL 10<br />
UM007701-1100
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