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<strong>eZ80</strong> <strong>CPU</strong><br />
User Manual<br />
140<br />
TST A, p<br />
Test<br />
Operation<br />
A • p<br />
Description<br />
The p operand is any of r, n, or (HL). The p operand is bitwise AND’ed with the<br />
contents of the Accumulator and the flags are set to 1. The contents of the<br />
Accumulator and the p operand are not altered.<br />
ADL mode affects operations with registers HL. ADL mode may be overridden<br />
with the .S or .L suffix.<br />
Condition Bits Affected<br />
S<br />
Z<br />
H<br />
P/V<br />
N<br />
C<br />
Set if result is negative; reset otherwise.<br />
Set if result is zero; reset otherwise.<br />
Set.<br />
Set if parity is even; reset otherwise.<br />
Reset.<br />
Reset.<br />
Mnemonic Operands ADL Mode Cycles Op Codes<br />
TST A,r X 2 ED, jj<br />
TST A,n X 3 ED, 64, nn<br />
TST A,(HL) X 3 ED, 74<br />
TST.S A,(HL) 1 4 52, ED, 74<br />
TST.L A,(HL) 0 4 49, ED, 74<br />
jj = binary code 00 rrr 100 where rrr identifies the A, B, C, D, E, H, or L<br />
register assembled as follows into the object code:<br />
Register<br />
rrr<br />
A 111<br />
B 000<br />
C 001<br />
D 010<br />
E 011<br />
H 100<br />
L 101<br />
UM007701-1100
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