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<strong>eZ80</strong> <strong>CPU</strong><br />
User Manual<br />
151<br />
Index<br />
A<br />
ADC A, s, 18<br />
ADC HL, ss, 19<br />
ADD A, s, 20<br />
ADD rr, ss, 21<br />
address generation<br />
ADL mode, 7<br />
native Z80 mode, 7<br />
virtual Z80 mode, 7<br />
addressing modes, 7<br />
Direct Address, 8<br />
Immediate, 7<br />
Indexed Addressing, 8<br />
Modified Page Zero, 7<br />
Register Addressing, 8<br />
Register Indirect Addressing, 8<br />
Relative Address, 8<br />
ADL bit operation, 3<br />
ADL exceptions, 12<br />
ADL mode, 8, 4<br />
changing, 9<br />
with CALL, 9<br />
with JP (rr), 11<br />
with JP nnnn, 10<br />
with RET, RETI, RETN, 11<br />
with RST nn, 10<br />
AND A, s, 22<br />
assembly language, 14<br />
B<br />
BIT b, m, 23<br />
C<br />
C Flag (definition), 14<br />
CALL cc, Mmn, 25<br />
CALL Mmn, 24<br />
CCF, 27<br />
CP A, s, 28<br />
CPD, 29<br />
CPDR, 30<br />
CPI, 31<br />
CPIR, 32<br />
CPL, 33<br />
<strong>CPU</strong> response<br />
maskable interrupts, 5<br />
non-maskable interrupts, 5<br />
vectored interrupts, 6<br />
D<br />
DAA, 34<br />
DEC m, 36<br />
DEC qq, 35<br />
DI, 37<br />
DJNZ d, 38<br />
E<br />
EI, 39<br />
EX (SP), rr, 42<br />
EX AF, AF’, 40<br />
EX DE, HL, 41<br />
EXX, 43<br />
<strong>eZ80</strong><br />
addressing modes, 7<br />
ADL and Mixed ADL, 8<br />
architectural overview, 1<br />
assembly language, 14<br />
<strong>CPU</strong> response, 5<br />
features, 1<br />
I/O space, 7<br />
UM007701-1100
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