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<strong>eZ80</strong> <strong>CPU</strong><br />
User Manual<br />
134<br />
SLA m<br />
Shift Left Arithmetic<br />
Operation<br />
CY 7 0<br />
0<br />
Description<br />
The m operand is any of A, B, C, D, E, H, L, (HL), (IX+d), or (IY+d). The<br />
contents of the m operand are shifted left one bit position. Bit 7 is copied into the<br />
Carry Flag and a zero is copied into Bit 0 of the m operand. ADL mode affects<br />
operations with register HL, IX, or IY. ADL mode may be overridden with the .S<br />
or .L suffix.<br />
Condition Bits Affected<br />
S<br />
Z<br />
H<br />
P/V<br />
N<br />
C<br />
m<br />
Set if result is negative; reset otherwise.<br />
Set if result is zero; reset otherwise.<br />
Reset.<br />
Set if parity is even; reset otherwise.<br />
Reset.<br />
Data from Bit 7 of the source.<br />
Mnemonic Operands ADL Mode Cycles Op Codes<br />
SLA r X 2 CB, kk<br />
SLA (HL) X 5 CB, 16<br />
SLA.S (HL) 1 6 52, CB, 16<br />
SLA.L (HL) 0 6 49, CB, 16<br />
SLA (IX+d) X 7 DD, CB, dd, 16<br />
SLA.S (IX+d) 1 8 52, DD, CB, dd, 16<br />
SLA.L (IX+d) 0 8 49, DD, CB, dd, 16<br />
SLA (IY+d) X 7 FD, CB, dd, 16<br />
SLA.S (IY+d) 1 8 52, FD, CB, dd, 16<br />
SLA.L (IY+d) 0 8 49, FD, CB, dd, 16<br />
kk = binary code 00 100 rrr where rrr identifies the A, B, C, D, E, H, or L<br />
register assembled as follows in the object code:<br />
Register rrr<br />
A 111<br />
B 000<br />
C 001<br />
D 010<br />
E 011<br />
H 100<br />
L 101<br />
UM007701-1100
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