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<strong>eZ80</strong> <strong>CPU</strong><br />
User Manual<br />
104<br />
OUTD2<br />
Output and Decrement HL<br />
Operation<br />
Description<br />
(BC) ← (HL)<br />
B ← B – 1<br />
C ← C – 1<br />
HL ← HL – 1<br />
The contents of the memory location specified by the HL are loaded into the<br />
<strong>CPU</strong>. This byte is then output to the I/O address specified by the BC register.<br />
The B, C, and HL registers are decremented.<br />
ADL mode affects operations with the HL register. ADL mode may be<br />
overridden with the .S or .L suffix.<br />
Condition Bits Affected<br />
S<br />
Z<br />
H<br />
P/V<br />
N<br />
C<br />
Not affected.<br />
Set if B = 0; reset otherwise.<br />
Not affected.<br />
Not affected.<br />
Set.<br />
Not affected.<br />
Mnemonic Operands ADL Mode Cycles Op Codes<br />
OUTD2 — X 5 ED, AC<br />
OUTD2.S — 1 6 52, ED, AC<br />
OUTD2.L — 0 6 49, ED, AC<br />
UM007701-1100
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