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<strong>eZ80</strong> <strong>CPU</strong><br />
User Manual<br />
129<br />
RST n<br />
Restart<br />
Operation<br />
—<br />
Description<br />
ADL Prefix Operation<br />
0 None Stack 2-byte logical return address using SPS mapped by MBASE.<br />
Keep ADL cleared to 0. Load the 16-bit logical address 00nn into PC.<br />
1 None Stack 3-byte return address using SPL.<br />
Keep ADL set to 1. Load the 24-bit address 0000nn into PC.<br />
0 .IS Stack 2-byte logical return address using SPS mapped by MBASE.<br />
Stack a 00 byte using SPL. Keep ADL cleared to 0.<br />
Load the 16-bit logical address 00nn into PC.<br />
1 .IS Stack the two LS bytes of return address using SPS mapped by MBASE .<br />
Stack an MS byte of return address using SPL.<br />
Stack a 01 byte using SPL. Clear ADL to 0.<br />
Load the 16-bit logical address 00nn into PC.<br />
0 .IL Stack 2-byte logical return address using SPL.<br />
Stack a 01 byte using SPL. Set ADL to 1.<br />
Load the 24-bit address 0000nn into PC.<br />
1 .IL Stack 3-byte return address using SPL and keep ADL set to 1.<br />
Stack a 01 byte using SPL. Load the 24-bit address 0000nn into PC.<br />
Condition Bits Affected<br />
None<br />
Mnemonic Operands ADL Mode Cycles Op Codes<br />
RST p 0/1 * kk<br />
RST.IS p 0 * 40, C9<br />
RST.IL p 1 * 52, C9<br />
kk = binary code 11 ttt 111 where ttt identifies the low-order byte to be<br />
loaded into the PC assembled as follows in the object code:<br />
p<br />
ttt<br />
00H 000<br />
08H 001<br />
10H 010<br />
18H 011<br />
20H 100<br />
28H 101<br />
30H 110<br />
38H 111<br />
UM007701-1100
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