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<strong>eZ80</strong> <strong>CPU</strong><br />
User Manual<br />
101<br />
OTIR<br />
Output and Increment HL<br />
Operation<br />
Description<br />
repeat:<br />
{ (0,C) ← (HL)<br />
B ← B – 1<br />
HL ← HL + 1<br />
} while B ≠ 0<br />
The contents of the memory location specified by the HL are loaded into the<br />
<strong>CPU</strong>. This byte is then output to the I/O address specified by the C register with<br />
address (15-8) set to zero. The B register decrements and the HL register<br />
increments. The instruction repeats until the B register equals zero.<br />
ADL mode affects operations with the HL register. ADL mode may be<br />
overridden with the .S or .L suffix.<br />
Condition Bits Affected<br />
S<br />
Z<br />
H<br />
P/V<br />
N<br />
C<br />
Not affected.<br />
Set.<br />
Not affected.<br />
Not affected.<br />
Set.<br />
Not affected.<br />
Mnemonic Operands ADL Mode Cycles Op Codes<br />
OTIR — X 5/3 ED, B3<br />
OTIR.S — 1 6/3 52, ED, B3<br />
OTIR.L — 0 6/3 49, ED, B3<br />
UM007701-1100
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