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<strong>eZ80</strong> <strong>CPU</strong><br />
User Manual<br />
136<br />
SRA m<br />
Shift Right Arithmetic<br />
Operation<br />
7 0<br />
m<br />
CY<br />
Description<br />
The contents of the m operand are shifted right one bit position. The contents of<br />
Bit 0 are copied into the Carry Flag and the previous contents of Bit 7 are<br />
unchanged. ADL mode affects operations with the HL, IX, or IY register. ADL<br />
mode may be overridden with the .S or .L suffix.<br />
Condition Bits Affected<br />
S<br />
Z<br />
H<br />
P/V<br />
N<br />
C<br />
Set if result is negative; reset otherwise.<br />
Set if result is zero; reset otherwise.<br />
Reset.<br />
Set if parity is even; reset otherwise.<br />
Reset.<br />
Data from Bit 0 of the source.<br />
Mnemonic Operands ADL Mode Cycles Op Codes<br />
SRA r X 2 CB, kk<br />
SRA (HL) X 5 CB, 2E<br />
SRA.S (HL) 1 6 52, CB, 2E<br />
SRA.L (HL) 0 6 49, CB, 2E<br />
SRA (IX+d) X 7 DD, CB, dd, 2E<br />
SRA.S (IX+d) 1 8 52, DD, CB, dd, 2E<br />
SRA.L (IX+d) 0 8 49, DD, CB, dd, 2E<br />
SRA (IY+d) X 7 FD, CB, dd, 2E<br />
SRA.S (IY+d) 1 8 52, FD, CB, dd, 2E<br />
SRA.L (IY+d) 0 8 49, FD, CB, dd, 2E<br />
kk = binary code 00 101 rrr where rrr identifies the A, B, C, D, E, H, or L<br />
register assembled as follows in the object code:<br />
Register rrr<br />
A 111<br />
B 000<br />
C 001<br />
D 010<br />
E 011<br />
H 100<br />
L 101<br />
UM007701-1100