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<strong>eZ80</strong> <strong>CPU</strong><br />
User Manual<br />
111<br />
POP vv<br />
Pop Stack<br />
Operation<br />
Description<br />
if .L or (ADL and not .S)<br />
vv7-0 ← (SPL)<br />
vv15-8 ← (SPL+1)<br />
vv23-16 ← (SPL+2)<br />
SPL ← SPL + 3<br />
else<br />
vv7-0 ← (SPL)<br />
vv15-8 ← (SPL+1)<br />
SPS ← SPS + 2<br />
The vv operand is any of AF, BC, DE, HL, IX, or IY. In ADL mode, the three<br />
bytes at the memory location specified by the contents of SPL are loaded into<br />
the 24-bit vv register and the SPL increments by three. In non-ADL mode, the<br />
two bytes at the memory location specified by the contents of SPS are loaded<br />
into the 16-bit vv register and SPS increments by two. POP IX or POP IY in non-<br />
ADL mode results in the IX(23-16) or IY(23-16) being reset to zero. ADL mode<br />
affects operations with the AF, BC, DE, HL, IX, IY, or SP register. ADL mode<br />
may be overridden with the .S or .L suffix.<br />
Condition Bits Affected<br />
Mnemonic Operands ADL Mode Cycles Op Codes<br />
POP ss 0/1 3/4 kk<br />
POP.S ss 1 4 52, kk<br />
POP.L ss 0 5 49, kk<br />
POP IX 0/1 4/5 DD, E1<br />
POP.S IX 1 5 52, DD, E1<br />
POP.L IX 0 6 49, DD, E1<br />
POP IY 0/1 4/5 FD, E1<br />
POP.S IY 1 5 52, FD, E1<br />
POP.L IY 0 6 49, FD, E1<br />
kk = binary code 11 ss0 001 where ss identifies the AF, BC, DE, or HL register<br />
assembled as follows into the object code:<br />
Register ss<br />
AF 11<br />
BC 00<br />
DE 01<br />
HL 10<br />
UM007701-1100
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