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<strong>eZ80</strong> <strong>CPU</strong><br />
User Manual<br />
93<br />
OR A, s<br />
Logical OR<br />
Operation<br />
Description<br />
A ← A ∨ s<br />
The s operand is any of r, n, (HL), (IX+d), or (IY+d). The s operand is logically<br />
OR’ed to the contents of the Accumulator where the result is stored. ADL mode<br />
affects operations with the HL, IX, and IY registers. ADL mode may be<br />
overridden with the .S or .L suffix.<br />
Condition Bits Affected<br />
S<br />
Z<br />
H<br />
P/V<br />
N<br />
C<br />
Set if result is negative; reset otherwise.<br />
Set if result is zero; reset otherwise.<br />
Set if carry from Bit 3; reset otherwise.<br />
Set if parity is even; reset otherwise.<br />
Reset.<br />
Reset.<br />
Mnemonic Operands ADL Mode Cycles Op Codes<br />
OR A,r X 1 jj<br />
OR A,n X 2 F6, nn<br />
OR A,(HL) X 2 B6<br />
OR.S A,(HL) 1 3 52, B6<br />
OR.L A,(HL) 0 3 49, B6<br />
OR A,(IX+d) X 4 DD, B6, dd<br />
OR.S A,(IX+d) 1 5 52, DD, B6, dd<br />
OR.L A,(IX+d) 0 5 49, DD, B6, dd<br />
OR A,(IY+d) X 4 FD, B6, dd<br />
OR.S A,(IY+d) 1 5 52, FD, B6, dd<br />
OR.L A,(IY+d) 0 5 49, FD, B6, dd<br />
jj = binary code 10 110 rrr where rrr identifies the A, B, C, D, E, H, or L<br />
register assembled as follows into the object code:<br />
Register rrr<br />
A 111<br />
B 000<br />
C 001<br />
D 010<br />
E 011<br />
H 100<br />
L 101<br />
UM007701-1100
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