eZ80 CPU - writeframeofmind.biz

eZ80 CPU
User Manual
6
Mode 2
This is the most powerful interrupt response mode. With this mode, you can
maintain a table of 16-bit starting addresses for every interrupt service routine.
This table may be located anywhere within the first 64K of memory. When an
interrupt is accepted, the interrupting device places the lower eight bits of the
interrupt vector on the data bus during the interrupt acknowledge cycle (Bit 0 is
assumed to be zero). The actual vector address consists of Bits 23-16 as zero,
Bits 15-8 are the contents of the I register, and Bits 7-0 are supplied vector byte.
The 16-bit word at the above vector address is fetched and its value is the
beginning of the interrupt service routine with Bits 23-16 provided by the eZ80
processor as zeros.
In ADL mode, the interrupt table must always be in the first 64KB, as must the
start of interrupt service routines entered through the interrupt table.
Vectored Interrupts
Vectored interrupts operate the same as Mode 2 interrupts no matter which
interrupt mode is selected. In the case of the vectored interrupt response, the
CPU fetches the low-order interrupt vector address not from the data bus, but
from the ivedct bus. The vectored interrupt source is used exclusively for
on-chip peripherals.
Illegal Instruction Traps
Interrupts and Traps
The eZ80 instruction set does not cover all possible sequences of binary
values. Sequences for which no operation is defined, are illegal instructions.
When an eZ80 processor fetches one of these sequences, it performs a Trap
sequence. The byte of the multi-byte instruction that caused the trap is indicated
by the Trap register. The Trap register is not part of the eZ80 CPU, so you must
refer to the eZ80 Product Specification for its Trap register configuration. An
instruction trap resets the Program Counter (PC) to zero.
Applications that only operate in Native Z80 mode or ADL mode are relatively
simple with respect to interrupts and traps. In these modes, memory always
starts at the beginning of the eZ80's potential 16MB memory space and the
interrupt and trap locations are never mapped. This means applications that
switch between modes or operate in Virtual Z80 mode, can simplify interrupts
and trap-handling by executing a STMIX instruction to set the mixed ADL bit. If
the mixed ADL bit is set to 1, interrupts and instruction traps stack the ADL
state, as well as the PC, and enter ADL mode in the first 64KB of the eZ80's
potential 16MB memory space.
UM007701-1100